Modified Zynq base TRD for Zybo

[Anant]

Hi,

 

I intend to modify the Zynq base TRD available on xilinx website. My objectives are-

1. To build the sobel filter application (as shown here) for zybo.
2. To have both hardware and software accelerators for sobel (or any) operation running on Zybo.
3. Have one of the ARM cores acting as Master, another ARM core and FPGA acting as Slaves for processing the data.

Luckily, I looked at an excellent demo on zybo, which helped me put first step forward. I have built the sources for the demo in Xilinx PlanAhead. However, the demo used only FPGA to do the sobel filtering, with no software acceleration. I was looking for something that could offload process consuming tasks on FPGA while retaining other tasks on ARM core. It appears the TRD is the right choice. Based on the experience I gained, I have started configuring the PL (FPGA) first in Xilinx PlanAhead.

 

I have some questions regarding this:

1. Is it really possible to port entire functionality of base TRD on Zybo? As zybo's zynq chip has lesser resources (LUTs, Flipflops, BRAMs etc.) compared to that of zc702 board/zedboard.
2. Are there any other functional limitations (clocks/ IO peripherals etc.) which may not allow to port the entire TRD on zybo?
3. If resources are constraints, then I'm ready to trim down the design but retaining the idea of having HW and SW accelerators together. Any idea, which functionalities of TRD could be trimmed down.

I read somewhere that, zybo can only use 720p stream as input compared to 1080p available through FMC on zc702 board/zedboard, but, that is ok with me.

 

I appreciate your answers/advices/guidelines in advance.

 

Thank you!

-Anant

 

 

[nicanor5]

Hello, have you found a tutorial on how to work with both CPUs on Zybo?

Thank you.