Pmod i2s with internal SCLK

[kumards]

Hello All,

I tried the program given in http://hamsterworks.co.nz/mediawiki/index.php/Pmodi2s

but there is no output on the SD.

I have simulated the clock with 100MHz and got these values.

clk 10ns 100Mhz
Sclk 1.56Mhz
mclk 40ns 25Mhz

SD is always zero in-spite of setting the input data_l and data_r as Ones as shown in picture and simulation output files.

I am unable to find the cause for the problem. Am i missing anything in testbench code, as I am simulating only CLK ?

What changes are to be made in that code if i have to use internal SCLK.

I have a PCB in which is  spartan 6 FPGA is hardwired to CS4344, leaving SCLK as open/NC.

I tried commenting SCLK signals and ran program but it didnt help either.

Kindly help to resolve.

Thanks in advance.

Kotresh Kumar

 

isim for i2s.wcfg

[artvvb]

@kumards

Could you provide simulation results for the signals internal to the i2s_output module? The process to set this up in Vivado, which should be the same would be to click on the drop down arrow next to i2s_test in the "Instances and Processes" subwindow, right click on the i2s_output instance within it, and select "Add to Wave Window". Then you will need to rerun your simulation to get waveforms for the signals that are not inputs or outputs.

Specifically, I notice that the "accepted" pin is never going high, so there may be an issue with your internal signals not having an initial state, or something else. It will be much easier to tell what the problem is if you look at the intermediate signals that the outputs are derived from. Not having an initial state is more of a problem in simulation than in a programmed design.

Edit: you can ignore the part about initial state, I reread the vhdl and this is not an issue.

Thanks,

Arthur