XADC simulation analog waveform / DRP interface

[jacobfeder]

I am trying to create a simple design that reads an analog waveform from the XADC. Can some explain how exactly to do this? I'm a bit confused about how the interface works. I've read through the XADC and XADC wizard documents from Xilinx. I set up my project with the XADC wizard and created a test bench shown below. When I run the sim, it says 

"Warning: The analog data file design.txt for XADC instance tb.xadc.inst was not found." I configured the XADC wizard to generate a sine wave for sim (also see below for the XADC settings that the wizard generated).The Xilinx XADC wizard document shows the analog waveform being displayed in the sim, but doesn't explain how to set that up (https://www.xilinx.com/support/documentation/ip_documentation/xadc_wiz/v3_0/pg091-xadc-wiz.pdf page 44). The simulation shows the XADC digital output always being 0. I'm not sure if it's a problem with the design.txt or the way I'm interfacing with the DRP port. I read on another forum that the enable port needs to be periodically enabled, but that doesn't really make much sense to me. My understanding is that the DRP port is for writing to the XADC internal registers that change its configuration. Is that correct? How do I need to interact with the DRP port in order for it to sample data? Clearly I'm missing something simple here.

Thanks!

 

module tb();
    localparam T=10;
    reg clk;
    
    always begin
        clk = 1'b1;
        #(T/2);
        clk = 1'b0;
        #(T/2);
    end
       
    reg enable;
    always begin
        enable = 1'b1;
        #T;
        enable = 1'b0;
        #(15*T);
    end
    wire data_ready;
    wire [15:0] xadc_data_out;
    reg [11:0] xadc_data;
    wire eoc;
    
    xadc_wiz_0 xadc (
        .daddr_in(),
        .den_in(enable),
        .dwe_in(),
        .di_in(),
        .busy_out(),
        .drdy_out(data_ready),
        .do_out(xadc_data_out),
        .dclk_in(clk),
        .reset_in(rst),
        .vp_in(),
        .vn_in(),
        .vauxp6(),
        .vauxn6(),
        .channel_out(),
        .eoc_out(eoc),
        .alarm_out(),
        .eos_out()
    );

    always @(posedge data_ready) begin
        xadc_data <= xadc_data_out[11:0];
    end
    
endmodule

XADC #(
        .INIT_40(16'h0416), // config reg 0
        .INIT_41(16'h31AF), // config reg 1
        .INIT_42(16'h0400), // config reg 2
        .INIT_48(16'h0100), // Sequencer channel selection
        .INIT_49(16'h0000), // Sequencer channel selection
        .INIT_4A(16'h0000), // Sequencer Average selection
        .INIT_4B(16'h0000), // Sequencer Average selection
        .INIT_4C(16'h0000), // Sequencer Bipolar selection
        .INIT_4D(16'h0000), // Sequencer Bipolar selection
        .INIT_4E(16'h0000), // Sequencer Acq time selection
        .INIT_4F(16'h0000), // Sequencer Acq time selection
        .INIT_50(16'hB5ED), // Temp alarm trigger
        .INIT_51(16'h57E4), // Vccint upper alarm limit
        .INIT_52(16'hA147), // Vccaux upper alarm limit
        .INIT_53(16'hCA33),  // Temp alarm OT upper
        .INIT_54(16'hA93A), // Temp alarm reset
        .INIT_55(16'h52C6), // Vccint lower alarm limit
        .INIT_56(16'h9555), // Vccaux lower alarm limit
        .INIT_57(16'hAE4E),  // Temp alarm OT reset
        .INIT_58(16'h5999), // VCCBRAM upper alarm limit
        .INIT_5C(16'h5111),  //  VCCBRAM lower alarm limit
        .INIT_59(16'h5555), // VCCPINT upper alarm limit
        .INIT_5D(16'h5111),  //  VCCPINT lower alarm limit
        .INIT_5A(16'h9999), // VCCPAUX upper alarm limit
        .INIT_5E(16'h91EB),  //  VCCPAUX lower alarm limit
        .INIT_5B(16'h6AAA), // VCCDdro upper alarm limit
        .INIT_5F(16'h6666),  //  VCCDdro lower alarm limit
        .SIM_DEVICE("ZYNQ"),
        .SIM_MONITOR_FILE("design.txt")
)

 

[jpeyron]

Hi @jacobfeder,

Here is a Xilinx forum thread that talks about issues with simulating the xadc and adding the design.txt in VIVADO as simulation source. I do not believe we have a simulation of the xadc but we do have a project for the arty for the xadc that is in verilog here.

cheers,

Jon

[jacobfeder]

Thanks!! For the benefit of anyone else having issues with this:

Adding the design.txt as a simulation source fixed it. I also had to make sure I was reading the correct address pin.

module tb();
    localparam T=10;
    reg clk;
    
    always begin
        clk = 1'b1;
        #(T/2);
        clk = 1'b0;
        #(T/2);
    end

    wire enable;  
    wire ready;
    wire [15:0] xadc_raw_out;
    wire [11:0] data;
    assign data = xadc_raw_out[15:4] + 12'b1000_0000_0000; // convert from signed to unsigned
    wire [4:0] ch;
    reg [6:0] addr = 6'h16;

   //xadc instantiation connect the eoc_out .den_in to get continuous conversion
    xadc_wiz_0 xadc
    (
        .daddr_in(addr),            // Address bus for the dynamic reconfiguration port
        .dclk_in(clk),             // Clock input for the dynamic reconfiguration port
        .den_in(enable),              // Enable Signal for the dynamic reconfiguration port
        .di_in(16'd0),               // Input data bus for the dynamic reconfiguration port
        .dwe_in(1'd0),              // Write Enable for the dynamic reconfiguration port
        .reset_in(1'd0),            // Reset signal for the System Monitor control logic
        .vauxp6(),              // Auxiliary channel 6
        .vauxn6(),
        .busy_out(),            // ADC Busy signal
        .channel_out(ch),         // Channel Selection Outputs
        .do_out(xadc_raw_out),              // Output data bus for dynamic reconfiguration port
        .drdy_out(ready),            // Data ready signal for the dynamic reconfiguration port
        .eoc_out(enable),             // End of Conversion Signal
        .eos_out(),             // End of Sequence Signal
        .alarm_out()           // OR'ed output of all the Alarms
    );         

endmodule

 

[farhanazneen]

hello sir @jacobfeder  and @jpeyron   what is  that design.txt  how did u created it please do let me know

[jacobfeder]

In the block diagram view use the XADC wizard it gives an option to create a design.txt which you can use or modify

[farhanazneen]

hello @jacobfeder  how to add design.txt please do let me know sir when i run the behavioural simulation im not getting any output and my input values representing xxx as my design.txt is not being read please do let me know how to add design.txt  file in simulation. The below are the pictures of simulation & design.txt file

 

[jacobfeder]

Why do you have 2 design.txt? Can we see the rest of the hierarchy? It's been awhile since I did this but I think you need to initialize it somehow.

[farhanazneen]

@jacobfeder  i just initialise the ip and after generation of output product i  got  2 design.txt files i dont know why

[jacobfeder]

Can you attach files or show how you initialized

[farhanazneen]

@jacobfeder sir this is how i initialise the IP below is the attachment. Iam  trying since more than one week i couldnt solve design.txt issue.

plz do let me know how to solve it .

 

[jacobfeder]

Firstly, start off simple and do a single channel measurement instead of channel sequencing. Second, your DCLK and RESET signals in the simulation seem to not be doing what they should be... I think you need to create a verilog/VHDL test bench.

[farhanazneen]

@jacobfeder sir the below is the  attachment of mainmodule and testbench please do let me know why i couldnt ge the proper output

xadc main.docx

xadc testbench.docx

[jacobfeder]

Not sure what's going wrong with yours. Below is the code I used. Hope it helps.

    wire xadc_conv_done;
    wire [15:0] xadc_data_wire;
    reg [15:0] xadc_data;
    always @(posedge clk) begin
        if (!m_axis_aresetn) begin
            xadc_data <= 0;
        end else begin
            if (xadc_conv_done) begin
                xadc_data <= xadc_data_wire;
            end
        end
    end
    xadc_wiz_0 adc (
      .m_axis_tvalid(xadc_conv_done),  // output wire m_axis_tvalid
      .m_axis_tready(1),  // input wire m_axis_tready
      .m_axis_tdata(xadc_data_wire),    // output wire [15 : 0] m_axis_tdata
      .m_axis_tid(),        // output wire [4 : 0] m_axis_tid
      .m_axis_aclk(clk),      // input wire m_axis_aclk
      .s_axis_aclk(clk),      // input wire s_axis_aclk
      .m_axis_resetn(m_axis_aresetn),  // input wire m_axis_resetn
      .vp_in(0),                  // input wire vp_in
      .vn_in(0),                  // input wire vn_in
      .vauxp6(analog_in_p),                // input wire vauxp6
      .vauxn6(analog_in_n),                // input wire vauxn6
      .channel_out(),      // output wire [4 : 0] channel_out
      .eoc_out(),              // output wire eoc_out
      .alarm_out(),          // output wire alarm_out
      .eos_out(),              // output wire eos_out
      .busy_out()            // output wire busy_out
    );
    

 

[farhanazneen]

@jacobfeder  sir my question is i simulated the xadc example project which is provided by xilinx with testbench but without the auxiliary or differential inputs but my question is now i want to simulate xadc ip with auxiliary inputs in vivado simulator i wrote test bench too but im getting errors . could u provide me test bench for auxiliary input to simulate in vivado simulator without using sdk. The below is the attachment of xadc example project of  output without input i would like to implement same but with auxiliary input plz do let me know sir how to proceed.

[farhanazneen]

@jacobfederxadc simulation issue never ends i was trying since past  3 weeks to simulate xadc with auxiliary input  vaux0 (zedboard xadc header pin) sinewave   but always stuck with the errors.Always there  is  warnings showing up  top module is not defined and undeclared parameters.I want  a testbech with drp interface of auxiliary input plz if u have do provide it