MGT on Nexys Video

[Matthew Sacco]

Hi,

I am having trouble locating the MGT data RX and TX differential pairs in the master constraints file provided from Digilent. The pins are present in the schematic but not in the constraints file. Could anyone suggest how I can locate these?

 

Thank you

NexysVideo_Master.xdc

[jpeyron]

Hi @Matthew Sacco,

The FMC Transceiver clocks MGT and GTP constraints are at the top of the xdc file right below ## Clock Signal on line 11-18. Here is the xdc on our Github as well.

[Matthew Sacco]

Yes, I am aware of the GTP constraints declared at the top of the XDC. I am more concerned on the actual differential RX and TX positive and negative ports instead of the clocks. These are ports which have to do with the GTP channel primitive however they are brought up to the transceiver core top layer and I think that they need to be constrained to a particular port on the board which should also be connected to the FMC connector.

Without me constraining these inputs (receiver) and outputs (transmitter) the design will not work.

I have read that in the constraints file there should also be the gtp_channel primitive itself declared but I am not quite sure how that works yet. 

[jpeyron]

Hi @Matthew Sacco,

The pins to be constrained are on sheet 10, pins D7,C7,D9,C9. I have reached out to more experienced engineers to see how they should be constrained in the xdc.

cheers,

Jon

[Matthew Sacco]

Hi @jpeyron,

I agree with you on locating the pins on sheet 10. I greatly appreciate the support! Looking forward to hearing about the XDC file.

[elodg]

See ug482 for information on GTP transceivers. The user guide has a whole section dedicated to the 7-series FPGA Transceiver Wizard, which is how you are expected to use the transceivers. The placement of the primitives is also done through that wizard. Each channel and clocking primitive is identified by an XY coordinate rather than pin designators.

If you do not wish to use the wizard, create the XDC manually and look up the pin designators in the schematic as @jpeyron showed above.

 

[Matthew Sacco]

Thanks @elodg for the reply. Having said that, I am still unsure on what to do with the RXN_IN, RXP_IN and TXN_OUT and TXP_OUT signals which are created by the wizard itself. Now, I am starting to think that these are just debugging ports however why would a debug signal be declared as an input?

 

 

[elodg]

See the example project for the IP generated by the Transceiver Wizard to see how these should be handled. The wizard should generate all the necessary constraints and the pins I believe should just be made external.

This is what I get in the example design:

##---------- Set placement for gt0_gtp_wrapper_i/GTPE2_CHANNEL ------
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt0_gtwizard_0_i/gtpe2_i]
##---------- Set placement for gt1_gtp_wrapper_i/GTPE2_CHANNEL ------
set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt1_gtwizard_0_i/gtpe2_i]

 

[Matthew Sacco]

What happens in the example design basically, the transmitter and receiver are connected together to serve as a loopback (in the testbench). In a real case scenario, I still have to see what to do. Will update this post with any new news.

[elodg]

Yes, in the test bench tx is assigned to rx. However, the example design is also implementable, and has the constraints for the transceiver channels. Isn't that what you were looking for?

[Matthew Sacco]

Yes, that is what I'm looking for. Implemented a raw example design from the IP core - resulted with failed timing. Not sure on which aspect to focus on to fix this problem. 

[jpeyron]

Hi @Matthew Sacco,

I am tagging @elodg in case he has not seen your follow up question.

cheers,

Jon

[elodg]

On 05/04/2017 at 7:05 PM, Matthew Sacco said:

Yes, that is what I'm looking for. Implemented a raw example design from the IP core - resulted with failed timing. Not sure on which aspect to focus on to fix this problem. 

Well, "failed timing" is like saying the sky is blue. You got to tell us more if you want help with that. Google Xilinx timing closure for more info.

Here is one link that is a good starting point: https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html