I downloaded the source HDL for a h.264 decoder from opencores.org. I'm trying to integrate this core into a video pipeline using the Zybo board. In order to use this core, I need it to be on the AXI4 bus. I'm trying to package the IP as an AXI4 peripheral using the Create and Package IP wizard, however I get errors. I've searched the Xilinx documentation for help as to what these might mean, buy I haven't found anything super helpful.
My Questions:
1. Is it possible to package this core as an AXI4 peripheral?
2. Can anyone explain, or point me to some documentation that can help me understand the errors shown in the picture image1?
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jasonbla20
Hello,
I downloaded the source HDL for a h.264 decoder from opencores.org. I'm trying to integrate this core into a video pipeline using the Zybo board. In order to use this core, I need it to be on the AXI4 bus. I'm trying to package the IP as an AXI4 peripheral using the Create and Package IP wizard, however I get errors. I've searched the Xilinx documentation for help as to what these might mean, buy I haven't found anything super helpful.
My Questions:
1. Is it possible to package this core as an AXI4 peripheral?
2. Can anyone explain, or point me to some documentation that can help me understand the errors shown in the picture image1?
Thank you,
Jason
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