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jasonbla20

Packaging an existing IP as AXI4 periperhal

Question

Hello,

I downloaded the source HDL for a h.264 decoder from opencores.org.  I'm trying to integrate this core into a video pipeline using the Zybo board.  In order to use this core, I need it to be on the AXI4 bus.  I'm trying to package the IP as an AXI4 peripheral using the Create and Package IP wizard, however I get errors.  I've searched the Xilinx documentation for help as to what these might mean, buy I haven't found anything super helpful. 

My Questions:

1. Is it possible to package this core as an AXI4 peripheral?

2. Can anyone explain, or point me to some documentation that can help me understand the errors shown in the picture image1?

 

Image1.thumb.JPG.1be3c773813e8e5505ab74afe862e2b7.JPG

 

Image2.thumb.JPG.e221492e59c84cd96b668e3c227fccc4.JPG

 

Thank you,

 

Jason

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@jasonbla20

Vivado is correct, your AXI interfaces aren't mapped, what this means is that there are no ports associated with them, a normal AXI ip would have a significant number of extra ports "inside" of the AXI interface (when you click the '+', extra pins should appear, where you just have the '-') fixing this manually is tedious and confusing, so I'd recommend that you start from here. I believe that you may have created your ip core with your hdl as the top module, instead of wrapping it in an AXI module - pay special attention to steps 2-5 of the tutorial.

As an additional note, you will need to decide how your hdl should be controlled by the processor, if it needs to run quickly, AXI may not be the right solution. You can have some of your inputs controlled by other hdl, with others controlled by the processor, but deciding which should be which is a design question that I can't really answer, mostly it depends on how fast the input needs to be updated.

Hope this helps,

Arthur

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Thank you for your reply.  In my video pipeline, I'm using AXI VDMA -> (decoder) -> AXI stream to video out -> rgb2vga -> vga display.  With all these cores being on the AXI4 bus, I assumed that the decoder must be also. I thought the AXI bus was the high performance bus on the zybo?

I did use the top module of the decoder hdl as the top module of the AXI4 peripheral. Can you explain why this is incorrect?

 

Thank you

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@jasonbla20

If you look at the tutorial that I linked in the previous post, the standard AXI wrapper has a number of AXI-related pins that are not included in your decoder source, you will need to modify this AXI wrapper to instantiate your decoder module and handle the decoder inputs and outputs. A normal AXI bus will include a number of different ports such as s_axi_aclk. Vivado will automatically include these in the AXI interface, but they still need to be there. What you are missing right now is the custom link between the AXI bus and your decoder hdl.

The potential issue with AXI is that it is fast, just maybe not 1080p 30fps pixel-by-pixel fast, I'm not sure.

Thanks,

Arthur

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