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Importing Custom IP VIvado 2016.2


Question

Hello,

I downloaded the verilog source files for a H.264 Decoder from opencores.org; I'm trying to integrate this decoder into a video pipeline on a Digilent Zybo board.  However, when I try to package this IP in Vivado 2016.2,  the GUI shows there is no ports.  I'm able to successfully package it, but it is useless because there is no i/o.  I've attached a few pictures from the Create and Package IP wizard to illustrate what I'm talking about.  If I click the port import dialog, as shown in the picture, nothing happens.  Does anyone have any suggestions as to how I can successfully import this IP in a form that is usable?

 

EDIT:

To clarify, the IP that I have is not an AXI4 peripheral.  Is there a way to take a non AXI4 IP and turn it into an AXI4 one that vivado can understand?

 

Thanks,

Jason

 

Ports and Interfaces

 

Customization GUI

Edited by jasonbla20
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Hi @jasonbla20,

Here and here are good tutorials for making a custom IP. Looking at your screen shots the name of the file is nova_tb.v which usually means its a test bench file. I have not made a test bench into an IP before. If you are not able to make the encoder into and IP than if the encoder (not test bench code) is in HDL then you should be able to use the add block feature in the Vivado 2016.x with an axi gpio IP block like the attached project. 

cheers,

Jon

GPIO_add_a_block.zip

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13 minutes ago, jpeyron said:

Hi @jasonbla20,

Here and here are good tutorials for making a custom IP. Looking at your screen shots the name of the file is nova_tb.v which usually means its a test bench file. I have not made a test bench into an IP before. If you are not able to make the encoder into and IP than if the encoder (not test bench code) is in HDL then you should be able to use the add block feature in the Vivado 2016.x with an axi gpio IP block like the attached project. 

cheers,

Jon

GPIO_add_a_block.zip

Thanks for your reply.  I will check out those linked tutorials when I have a moment.  I believe the nova_tb.v is the top module of the verilog project.  Here a diagram from the documentation:

Diagram.JPG.143f93c95d3ee45a9b2aff5ba8046743.JPG

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