Warning during Implementation Basys2 board HELP please !

[Davelynch]

Hey every one!

 

I use Basys2 board spartan3E 100k with Active HDL of ALDEC to study digital design.

 

I have meet a problem when I try to implement my VHDL code the Implementation is ended and I have this message : "Warning: Implementation ended with warning(s)."

 

In the Implementation report I have something like that :  "ConstraintSystem - A target design object for the Locate constraint
   '<NET "an<3>" LOC = "k14";> [sw2led.ucf(37)]' could not be found and so the
   Locate constraint will be removed."

 

I have tried to figure out but I don't know where the warning come from : my design is very easy , it consist just to turn on Led with slipe switch.

I think the problem can come from ucf file but why? I have choose the ucf fitted to my design.

 

Have you ever met this kind of problem?

 

Help please!!

 

I have attached my project if you want to see.

 

Thanks

 

 

 

 

Example1.zip

[JColvin]

Yep, that's what you needed to do.   

I believe you could have also just commented out the pins you weren't using and that should also get your design up and running as well.

 

Thanks,

JColvin

[hamster]

The HDL compiler has a global view of things, as everything ends up completely mapped down onto the physical hardware. This allows for a higher level of optimization than can be done by optimizing compilers, The tools like to brag about this by raising warnings. Examples are:

 

* If a register's output is not connected because I higher-level module doesn't make use it, and it can then be removed from the design. So if you hook a 24-bit VGA signals to a  12-bit VGA output, then you will get a lot of warning that "register red(3) [and others] are not used - removing".

 

* Likewise if you make a 10-bit counter, and only use the top bit then you will get nine warnings that "register counter(x) is not used"

 

* If you use an external pin as clock signal, and it isn't one of the preferred clock pin then you will get a warning.

 

* If you don't wire up the reset port on a PLL clocking resources you get warnings that things might go awry if the clock ever stops, as the PLL will drop out of locked state and not relock.

 

* If you have pull-up resistor enabled on pin that is only ever used as an output you will get a warning

 

* Warnings like "Oh, it you initialised that with 1s I could optimize this register away!"

 

* Other warnings like "You haven't initialized that register - I'm going to pick zeros, have a nice day".

 

These sorts of warnings are the "roadside signs" letting you know what is going on, and should on deeper inspection make sense.

 

Then we have the other sorts of warnings, where you really should address them. Examples are

 

* Missing variables on process sensitivity lists (a VHDL thing).

 

* If you use a design pattern that produces sub-optimal performance (like using boolean logic on a signal used for clocking - aka "gating the clock") then you will get a warning.

 

and so on. After you've used FPGAs for a while you will get a feel for what is important and what isn't.

[Davelynch]

It ' s me again for mo information this is VHDL code :

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;


entity sw2led is
  port(
       sw : in STD_LOGIC_VECTOR(7 downto 0);
       ld : out STD_LOGIC_VECTOR(7 downto 0)
  );
end sw2led;

architecture sw2led of sw2led is

---- Signal declarations used on the diagram ----



begin

---- Terminal assignment ----

    -- Inputs terminals
	ld <= sw;

    -- Outputbuffer terminals
	

end sw2led;

and this the content of my ucf file :

# Pin assignment for LEDs
NET "ld<7>" LOC = "g1" ; 
NET "ld<6>" LOC = "p4" ; 
NET "ld<5>" LOC = "n4" ; 
NET "ld<4>" LOC = "n5" ; 
NET "ld<3>" LOC = "p6" ; 
NET "ld<2>" LOC = "p7" ; 
NET "ld<1>" LOC = "m11" ; 
NET "ld<0>" LOC = "m5" ; 

# Pin assignment for slide switches
NET "sw<7>" LOC = "n3"; 
NET "sw<6>" LOC = "e2"; 
NET "sw<5>" LOC = "f3"; 
NET "sw<4>" LOC = "g3"; 
NET "sw<3>" LOC = "b4"; 
NET "sw<2>" LOC = "k3"; 
NET "sw<1>" LOC = "l3"; 
NET "sw<0>" LOC = "p11"; 

# Pin assignment for pushbutton switches
NET "btn<3>" LOC = "a7"; 
NET "btn<2>" LOC = "m4"; 
NET "btn<1>" LOC = "c11"; 
NET "btn<0>" LOC = "g12"; 

# Pin assignment for 7-segment displays
NET "a_to_g<6>"  LOC = "l14"  ;
NET "a_to_g<5>"  LOC = "h12"  ;
NET "a_to_g<4>"  LOC = "n14"  ;
NET "a_to_g<3>"  LOC = "n11"  ;
NET "a_to_g<2>"  LOC = "p12"  ;
NET "a_to_g<1>"  LOC = "l13"  ;
NET "a_to_g<0>"  LOC = "m12"  ;
NET "dp"  LOC = "n13"  ;

NET "an<3>" LOC = "k14"; 
NET "an<2>" LOC = "m13"; 
NET "an<1>" LOC = "j12"; 
NET "an<0>" LOC = "f12"; 

# Pin assignment for clock
NET "clk" LOC = "b8"; 
 

[Davelynch]

Finally I have found what is the problem : I have just keep pin what I need in my ucf file and I have delete rest

[Davelynch]

Yes you are right JColvin : I have commented out unused pins.

 

Thanks

[hamster]

Another thing is that "warnings" in FPGA-land has a different meaning to "warnings" in software-land.

 

In FPGA-land compiler warnings are more like a roadside sign asking you to "slow down", or "slippery when wet". It is telling you where things are not as would be normally expected, but not in themselves particularly dangerous. You would expect to see them, and pay attention to them when appropriate, but most of the time they are informational only. 

 

In software-land compiler warnings are like your mother - "I'm warning you not to do that!", "Do you really think that this is a good idea?", "If you keep this up there will be trouble, and it will be your fault!". Those sorts of warnings are best acted on, or avoided completely.

 

However, if you go round a slippery corner at twice the posted limit while it is raining you can expect that bad things are going to happen - and you can be sure that there was always a warning sign telling you not to do that :-)

[Davelynch]

I don't really undestantd : for you what is the difference between FPGA-land compiler and software-land compiler ?

 

But I think warning in Active HDL synthesys is like mother warning because you need just one warning then you can validate your synthesys