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Problem with ucf file

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I am compiling a simple tutorial example for the Basys2  on the Xilinx project navigator and I get the following error message regarding my ucf file. I used the same ucf file for other programs and it worked.

 

WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "ld<7>" LOC = "G1" ;> [gates2.ucf(1)]' could not be found and so the
   Locate constraint will be removed.
WARNING:ConstraintSystem - A target design object for the Locate constraint
   '<NET "ld<6>" LOC = "P4" ;> [gates2.ucf(2)]' could not be found and so the
Locate constraint will be removed.
 
-------
etc. 
 
the code is below
 
any assistance would be appreciated.
 
-- Example 1b: 2-input gates
 -- Copyright 2009, 2012 LBE Books, LLC
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gates2_top is
	 port(
		 sw : in STD_LOGIC_VECTOR(1 downto 0);
		 ld : out STD_LOGIC_VECTOR(5 downto 0)
	     );
end gates2_top;
							
architecture gates2_top of gates2_top is
component gates2 is
	 port(
		 a : in STD_LOGIC;
		 b : in STD_LOGIC;
		 z : out STD_LOGIC_VECTOR(5 downto 0)
	     );
end component;
begin

c1 : gates2
	port map(
		a => sw(1),
		b => sw(0),
		z => ld
	);	

end gates2_top;
 
-- Example 1: 2-input gates	
-- Copyright 2009, 2012 LBE Books, LLC
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity gates2 is
	 port(
		 a : in STD_LOGIC;
		 b : in STD_LOGIC;
		 z : out STD_LOGIC_VECTOR(5 downto 0)
	     );
end gates2;

architecture gates2 of gates2 is
begin
	z(5) <= a and b;
	z(4) <= a nand b;
	z(3) <= a or b;
	z(2) <= a nor b;
	z(1) <= a xor b;
	z(0) <= a xnor b;
end gates2;

 
--  ucf file

NET "ld<7>" LOC = "G1" ; # Bank = 3, Signal name = LD7
NET "ld<6>" LOC = "P4" ; # Bank = 2, Signal name = LD6
NET "ld<5>" LOC = "N4" ;  # Bank = 2, Signal name = LD5
NET "ld<4>" LOC = "N5" ;  # Bank = 2, Signal name = LD4
NET "ld<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3
NET "ld<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2
NET "ld<1>" LOC = "M11" ; # Bank = 2, Signal name = LD1
NET "ld<0>" LOC = "M5" ;  # Bank = 2, Signal name = LD0


NET "sw<7>" LOC = "N3";  
NET "sw<6>" LOC = "E2";  
NET "sw<5>" LOC = "F3"; 
NET "sw<4>" LOC = "G3"; 
NET "sw<3>" LOC = "B4";  
NET "sw<2>" LOC = "K3";  
NET "sw<1>" LOC = "L3";  
NET "sw<0>" LOC = "P11"; 

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I found the error.  I had used Led<n> like it is in the  "Basys2_100_250General.ucf"   file supplied by Digilent. 

It should be Ld<n> as used in my code and silkscreened on the Basys2 board.

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NET "Led<5>" LOC = "N4" ; # Bank = 2, Signal name = LD5 
NET "Led<4>" LOC = "N5" ; # Bank = 2, Signal name = LD4 
NET "Led<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3 
NET "Led<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2 
NET "Led<1>" LOC = "M11" ; # Bank = 2, Signal name = LD1 
NET "Led<0>" LOC = "M5" ; # Bank = 2, Signal name = LD0

NET "sw<1>" LOC = "L3"; # Bank = 3, Signal name = SW1 
NET "sw<0>" LOC = "P11"; # Bank = 2, Signal name = SW0


ERROR:ConstraintSystem:59 - Constraint <NET "Led<5>" LOC = "N4" ;> [gates2.ucf(1)]: NET "Led<5>" not found.  Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. 
ERROR:ConstraintSystem:59 - Constraint <NET "Led<4>" LOC = "N5" ;> [gates2.ucf(2)]: NET "Led<4>" not found.  Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. 
ERROR:ConstraintSystem:59 - Constraint <NET "Led<3>" LOC = "P6" ;> [gates2.ucf(3)]: NET "Led<3>" not found.  Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. 
ERROR:ConstraintSystem:59 - Constraint <NET "Led<2>" LOC = "P7" ;> [gates2.ucf(4)]: NET "Led<2>" not found.  Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. 
ERROR:ConstraintSystem:59 - Constraint <NET "Led<1>" LOC = "M11" ;> [gates2.ucf(5)]: NET "Led<1>" not found.  Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. 
ERROR:ConstraintSystem:59 - Constraint <NET "Led<0>" LOC = "M5" ;> [gates2.ucf(6)]: NET "Led<0>" not found.  Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file.

I tried the attached ucf file that I modified per your suggestions.

I still get an error message above.  the errors only involve the led  ld  which has no number enclosed in parenthesis.

 

sorry but the messge board would not allow me to insert files below this message.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Your design are only using a couple of the switches and 6 of the LEDs. If you comment or delete the unused ones the errors will go away.

Or just use them for something. :-)

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