Place design Error(During implementation stage)

[Aditya Gedela]

I want to generate a random number using ZYBO and vivado in verilog ....

First I tried using $random and $urandom function but later I came to know that it is not synthesizable in vivado.... So Now I tried to use LFSR algorithm for generating random number ...from the below link:

http://simplefpga.blogspot.in/2013/02/random-number-generator-in-verilog-fpga.html

 

Even then I get Errors:

[Place 30-494] The design is empty

[Common 17-69] Command failed: Placer could not place all instances

 I am getting place design ERROR after completion of 50% of implementation of design

Can anyone please get me out of this??

 

Thanks in advance...

[D@n]

@Aditya Gedela,

What are you using for an XDC file, and ... did you tell Vivado about the XDC file you were using?  i.e., did you add it to your project?

Dan

[Aditya Gedela]

Thanks @D@n .....

But this code doesn't require any .xdc constraints file.....As I am not using any internal clock or pmod pins.....

 

[D@n]

@Aditya Gedela,

You will also need to use the XDC file for buttons, switches, LEDs, audio, ethernet, video, etc.

Basically, the XDC file tells Vivado how to connect the FPGA to its external environment.  While I know there are such things as board support files that also help fill in here, ... I don't think that's going to help you.

So ... looking at that web page you pointed at, let me ask the quick question of which are you trying to place onto your board: the LFSR module or the test module?

And if (as I hope) the answer is the LFSR module, what are you connecting it to?  It requires a clock, a reset, and outputs.  If you are coming out of the board with that, what are you connecting these wires to?

Dan

[Aditya Gedela]

Thanks for your reply Sir @D@n

I actually created 2 source files and copied LFSR module code in one source file and test module code in another source file. Basically I am running test module code in which LFSR Object is called.

As there is no need of connecting board to generate the bitstream , I didn't connect ZYBO board to my laptop. And we can see that clock and reset are the registers created in test module so these are not from board....

 

[D@n]

@Aditya Gedela,

Hence ... your bug.

Sounds like you are trying to simulate something but hitting the synthesize button instead.

Anything you synthesize needs a top level design.  That top level must include a clock, and some I/O pins for the design.  It must also have an XDC file that maps the clock and I/O pins to external device pins.  Otherwise .... you have an empty design, and Vivado will just map all the pins to a high impedence state (i.e., the startup condition).

I think you want to simulate this design instead.  With simulation, you can create a pretend clock, pretend internal wires, and so forth ... and then see and plot what happens.  When you do this, though, your top level file tends to be a test bench file with no connections to the outside world.  You need to explain that to Vivado too--it's a simulation only file.

That should help move you forward,

Dan