Jump to content
  • 0

FPGA -ADC interface


Ananthan

Question

Hello,

I am trying to interface FPGA and adc..

 

 From the data sheet of ADC it is given that. when cs (chip select) active low ADC start conversion at the rising edge and for subsequent 14 serial clk (falling edge ) it will give 12 bits with two leading zeros and once 14 serial clock (falling edge) completed in the next rising edge the data should be transferred.

I this regard kindly clarify the following question

1. Shall I use rising edge  for the total process?

2. whether I should use only falling edge for conversion?

help me!

Thank you

Link to comment
Share on other sites

9 answers to this question

Recommended Posts

Thank you for your response

This is my verilog code Please correct me: not getting output

 

// PROGRAM TO INTERFACE ADC 7266 WITH VIRTEX-4 FPGA
// ADC WILL GIVE 14 BITS WITH TWO LEADING ZEROS IN EVERY 14 SCLK
//------------------------------------------------------
module adc_7266(clk,reset,adc_out,cs,data_out,sclk,ch_sl);
    input clk;
    input reset;
    input adc_out;   // SERIAL DATA FROM ADC TO FPGA
    
    
    output [11:0]data_out;
     output cs;
     output sclk;     // CLK FROM FPGA TO ADC @20MHZ
     output [2:0] ch_sl;
    
    wire   sclk;
    wire   q_time;    // QUIET TIME BETWEEN CONVERSION STOP AND START
    wire  adc_out;    
    wire [5:0] cnt_next;
    wire  [2:0] ch_sl;
    
   
    reg [12:0] data_next1;
    reg [11:0] data_out;
    reg [5:0] cnt_reg;
    reg       cs;        // CHIP SELECT ACTIVE LOW SIGNAL
    
      assign sclk=clk;
      assign ch_sl=3'b0;
      assign cnt_next=cnt_reg+1; //COUNTER FOR COVERSION TIME AND QUIET TIME
      assign soc = (cs==1'b0)&&(cnt_reg==6'd13)?1'b1:1'b0; // AFTER 14 SCLK THIS SIGNAL WILL GO HIGH
      assign q_time=(cs==1'b1)&&(cnt_reg==6'd43)?1'b1:1'b0; // QUITE TIME ENDS
      
      always@(posedge clk)
   begin
       cs<=0;
        if(reset==1'b1)
        begin
        cnt_reg<=0;
        //data_next1<=14'b1111_1111_1111_11;
         data_out<=12'b0;                         // CONVERSION STARTS
        end
        else if (soc==1'b1)
        begin
        data_out<=data_next1[11:0];  // DIGITAL DATA INPUT TO FPGA
        cnt_reg<=cnt_next;
        cs<=1;                 // CONVERSION STOPS
        end            
        else if (q_time==1'b1)   // CONVERSION STOP AND QUITE TIME IN PROGRESS
        begin
        cs<=0;                   // AGAIN PROCESS STARTS  
        cnt_reg<=0;   
        end
        else
        begin
        data_next1<={data_next1[11:0],adc_out};    // BIT BY BIT SHFITING SERIAL DATA FROM ADC
        cnt_reg<=cnt_next;
        end
    end
        
        
        
    
endmodule

 

Link to comment
Share on other sites

@Ananthan,

Ok, found the data sheet for what you are up to here.  Your 20MHz clock is well within the limits between 1MHz and 32MHz.  On page 22, you can find a diagram illustrating how the device is to be accessed.  Based upon that diagram, I would suggesting that you grab your inputs on the rising/positive edge of the clock.  I think that answers both questions you asked.

I might also suggest, though, that you don't use a logic clock that is locked to the ADC SPI clock speed.  While I don't recall seeing what FPGA you are actually using, from my background an 80MHz clock is a slow FPGA clock.  May I suggest that you run your SPI logic at the same speed as the rest of the FPGA, and just generate from this logic a SPI clock?  I think you'll have more control over the interface should you do this. 

Other things to pay attention to include the fact that the illustration shows CS transitioning, whether high or low, when the clock is high.

Just some things to think about,

Dan

Link to comment
Share on other sites

Thank you for your response.

Data sheet tells that adc doing conversion for every falling sclk

ie

cs =0 rising sclk

data conversion : falling edge

cs=1, data_out; rising edge

now my question should I count the data conversion time 14 sclk only at falling edge of sclk?

or does not matter shall I do same in rising edge

In the program I have counted the rising edge but not getting the output.

 

 

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...