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mmedrano

Arty SPI Module in Slave Mode

Question

Hi all,

I'm having trouble getting a spi module set to 'slave mode' to read data.  I'm working with the Arty Board and attached is my Vivado block diagram.  The SPI module that I'm having trouble with is 'axi_quad_spi_0'.  I've set the IP to be in standard and unchecked Master Mode in the SPI Options.  I set the FIFO to 256 and Freq Ratio 16x30.

I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing.

The other registers of axi_quad_spi_0 read as follows:

Reg 0x60 => 0x18a

Reg 0x64 => 0x25

Reg 0x70 => 0x01

whether or not the master device is sending SPI.  The output from these registers seem sort of reasonable, but I would hope the flag in reg 0x64 bit 5 to go to 0 in the case axi_quad_spi_0 clks spi data in, but it isn't, which is consistent with readreg 0x6C returning 0x00. 

I also tried connecting outputs of a master spi module to another slave spi module 'axi_quad_spi_2' and got the same result (see block diagram).  I've also tried, the xilinx spi polled mode examples and can't seem to get those working either.  See below for some relevant SDK code.  Can someone tell me what I might be doing wrong?  Is there something more fundamental that I don't understand?  Thanks!

Best,

Mike

http://tinypic.com/view.php?pic=2vmbjg6&s=9#.WNLezbIrJaQ

#define spi_dev_id2 XPAR_SPI_2_BASEADDR

void simple_receive() {
    int data;

    XSpi_WriteReg(spi_dev_id2,0x60,0x1EA);
    XSpi_WriteReg(spi_dev_id2,0x70,0x1);
    XSpi_WriteReg(spi_dev_id2,0x28,0x80);

    data = XSpi_ReadReg(spi_dev_id2,0x6C);
    printf("Lithe Buffer Simple %#02x\r\n",data);

}

 

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Hi @mmedrano,

Looking at your block design, The arty's  ui_clk coming out of the MIG is not suffecent to run the ext_spi_clk of the quad spi IP. I believe to fix this you should add a 3rd output clk from the clock wizard at 100 Mhz clock and connect all of the ext_spi_clk of the quad spi IP to it.

cheers,

Jon

 

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Thanks for the suggestion.  I tried generating 100 MHz through a third output on the clk wizard and connecting that to ext_spi_clk on the spi_lite ips but that didn't work..  I just got the same result as above.  Any other suggestions?

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Hi @mmedrano,

Could i get a screen shot of your current block design? I am not seeing anything else jump out at me. Could you attach a compressed copy of you project? Have you looked at our IP cores here? If you look at the bottom of our wiki you can see which Pmods use spi and how we connect them and the code used in sdk.  

cheers,

Jon

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Hey there,

Thanks again for the help and sorry for the late reply..  I still haven't had much luck working on this.  The project after compression is still too big to attach so, I just took snippets of the block diagram, constraints, and address editor in vivado.  I also included some relevant sdk code.  void main is in helloworld.c, but the spi_slave function is in spi_handler.c.

Just to be clear, I want the spi_slave module to be able to receive spi clk, ss, etc from some other master device.  As opposed to the spi_dac and spi_adc module which send and receive spi, but ultimately generate the clk and ss signals themselves.  

I looked at the links but it seems like all of them assume your spi module is configured to master as opposed to slave mode.  Is that right?

Thanks again for your help.

Best,

Mike

ADC_spi_sendreceive.c

ADC_spi_sendreceive.h

Capture_address_editor.PNG

Capture_blockdiagram.PNG

Capture_constraints.PNG

DAC_spi_send.c

DAC_spi_send.h

helloworld.c

spi_data.h

spi_handler.c

spi_handler.h

xparameters.h

 

EDIT:

Actually I found a way to share the project.  Please see the link: http://www.filedropper.com/arty-copy.  

Best,

Mike

Edited by mmedrano
Found way to share project

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Hi @mmedrano,

Here is a Xilinx forum thread that talks about having the SPISEL port connected to the slave select port of the SPI master. I see you have the SPISEL connected. Are you using this pin like it describes on page page 7 of the AXI Quad SPI v3.2 here).I would look at page 26, 78-81 of the AXI Quad SPI v3.2 as well.  I found some other threads about using slave mode with the axi quad spi  here and here. Also i would still use the output clock 3 for the ext_spi_clk in your design. I attached some screen shots of building a generic project using the PmodDA1 IP(SPI) below.

cheers,

Jon

AXI_QUAD_SPI_1.jpg

AXI_QUAD_SPI_2.jpg

AXI_QUAD_SPI_3.jpg

AXI_QUAD_SPI_4.jpg

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Thanks for the advice.  Googling spi slave and reading the forums and datasheets for the axi_spi ip were one of the first things i did..  I did connect the ext_spi_clk as you suggested, but still doesn't work.  It doesn't seem like too many people have explored the functionality of the spi ip in slave mode.  Has anyone here had slave mode in the axi quad spi (standard mode) working for them?  I'd really appreciate some input.

Best,

Mike

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Hi @mmedrano,

Unfortunately, I do not believe any of the forum moderators have used the AXI quad spi IP in slave mode before. So I will work on getting a basic project running with the AXI quad spi in slave mode. 

cheers,

Jon 

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Hi @mmedrano,

I have not finished the project but while making the Vivado design I think I found an issue with your slave axi spi IP set up. I believe your miso(master in slave out) ,mosi(master out slave in) and slave clk are going the wrong direction. I have attached screen shots of your axi slave spi IP and mine.

cheers,

Jon

AXI_QUAD_SPI_5.jpg

AXI_QUAD_SPI_6.jpg

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Hey thanks that was a good find.  It isn't clear to me that miso and mosi slave can share io0 but I think sck_i is probably the correct pin.  In any case, I just want to be able to read at this point, so mosi_slave is the relevant pin.  I played with the module in this configuration (and with ext_spi_clk changed to 50Mhz) and still haven't had much luck..  Were you able to find anything interesting?

Best,

Mike

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Hey all,

Might need a little more advice.  I'm very new to the arty so I really appreciate the help.  I find that each time I send SPI from the master device (zybo master rising edge 8 bit word), RxFifo (0x78) increments- which is what I expect.  However, when I read the SPI DRR receive register, (0x6C) the value returned is always 0x00.  

I've tried the polled spi example offered by sdk and i get the same result.  

Attached is a snapshot of my spi ip in vivado, the C code in sdk that I'm using, along with the output to the UART.  Any advice is appreciated. Thanks.

Best, 

Mike

 

Capture1.PNG

Capture2.PNG

Capture3.PNG

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Hi @mmedrano,

I haven't forgotten about this thread. I have not had a chance to work further on my slave spi project. I will dedicate some time tomorrow towards this project. Sorry about the delay.

thank you,

Jon

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Hi @mmedrano

I am working on the project still. I have not gotten it working. Have you tried using the debugger in sdk to see what happening once you get data from the Zybo?

thank you,

Jon

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Hi @mmedrano,

Unfortunately, I have not been able to get spi slave communication to work in SDK in my project. A co-worker made a project with the quad spi set as slave to see if they could help last week with no luck. Have you reached out to Xilinx's forums about this issue as well? 

thank you,

Jon

Edited by jpeyron

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Hi @mmedrano, did you ever get your SPI slave working?

I'm attempting the same thing and running into some issues with the IP core. Long story short, the core sometimes does not register data from the master - bit 0 in the status register at 0x64 remains 0, indicating RX FIFO is empty - despite what looks like a good SPI transaction on the logic analyzer.

Wondering if there were any tricks you used to get this working.

Thanks,

K

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