Follow-up - DDS Compiler 6.0 IP Core for audibie sinewave

[rb251415]

This is a response question to an earlier thread that I was not able to continue.

 

I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. 

"ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8"

I've tried it with 6, 8 and even all 32-bits and I get the same failure.

Code:

inst_1: dds_compiler_0
    port map ( aclk => clk,
               s_axis_phase_tvalid => '1',
               s_axis_phase_tdata => cntr(31 downto 24),  -- this is line 82 of Wave_top.vhd
               m_axis_data_tvalid => m_axis_data_tvalid,
               m_axis_data_tdata => m_axis_data_tdata);

 

LOG DATA:

Vivado Simulator 2016.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 0fc31941c582466d8f4474edc8fb8bef --debug typical --relax --mt 2 -L xbip_utils_v3_0_7 -L axi_utils_v2_0_3 -L xbip_pipe_v3_0_3 -L xbip_bram18k_v3_0_3 -L mult_gen_v12_0_12 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_3 -L xbip_dsp48_multadd_v3_0_3 -L dds_compiler_v6_0_13 -L xil_defaultlib -L secureip -L xpm --snapshot Wave_top_behav xil_defaultlib.Wave_top -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8 [C:/Users/Toshiba-/coregen_sinewave/coregen_sinewave.srcs/sources_1/new/Wave_top.vhd:82]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit wave_top in library work failed.

 

[D@n]

@rb251415,

Looking over what you just posted, I'm not seeing the problem.  Care to share any more of your problem?  Perhaps the problem exists some distance from your error?

Dan