kuangjiqingma Posted March 21, 2017 Share Posted March 21, 2017 Hi everyone; ZedBoard_OOB_Design offers us a hardware project xps_proj.I want to design a vdma image processing .So i add xapp1167 demo's hls ip and a vdma ip to xps_proj.But xps can't generate system.bit console:xflow done! touch __xps/system_routed xilperl E:/ISE_14.7/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par Analyzing implementation/system.par Done! system clk1 can't meet timing why this clk1 is 166.7mhz ?? Thank you! Link to comment Share on other sites More sharing options...
jpeyron Posted March 21, 2017 Share Posted March 21, 2017 Hi @kuangjiqingma, I haven't worked with XPS very much but could you post a screen shot of your block design and Errors/warning you are getting? Also if you are trying to use OpenCV here and here are forum threads that discuss Opencv with the Zedboard. thank you, Jon Link to comment Share on other sites More sharing options...
kuangjiqingma Posted March 22, 2017 Author Share Posted March 22, 2017 4 hours ago, jpeyron said: Hi @jpeyron I have solved this problem.I change vdma and fast_corner clk to 100M.so meeting timing. thank you, xin Link to comment Share on other sites More sharing options...
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kuangjiqingma
Hi everyone;
ZedBoard_OOB_Design offers us a hardware project xps_proj.I want to design a vdma image processing .So i add xapp1167 demo's hls ip and a vdma ip to xps_proj.But xps can't generate system.bit
console:xflow done!
touch __xps/system_routed
xilperl E:/ISE_14.7/14.7/ISE_DS/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
Analyzing implementation/system.par
Done!
system clk1 can't meet timing why this clk1 is 166.7mhz ??
Thank you!
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