Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?

[ailee]

I have a cheap Altera Cyclone II EP2C5T144C8 Dev Board and a few (4) of the IO/LVDS pins are shorted to VCC or GND as shown in the schematic segment below. The pins are also brought out to headers on the board.

The only things I can think of for why they are there are:

1. They are meant to be left non-populated (but were accidentally populated) for the user to add pull-up/pull-down resistors
2. They are somehow helping power the FPGA

Is there any reason a direct short to VCC/GND would be desirable for an IO pin on a Dev Board? Can I remove these resistors without negatively impacting the board's performance?

[Notarobot]

1) I would call these two pins as reference "1" and "0". It could be helpful if digital noise is high.

2) It might be useful to use along with differential pairs.

[D@n]

@ailee,

I tried to find the appropriate Altera manual, without much success.  Much as I hate to admit it, this forum is focused on Digilent FPGA boards, all of which contain Xilinx parts.  Have you considered posting on the Altera forum?  (This answer feels like such a cop-out ... sorry)

Dan