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Problem with Switches and push buttons on Zybo board


Aditya Gedela

Question

In this code, we are trying to make LEDS high when a push button and switches are pressed ...

 

My Code:

`timescale 1ns / 1ps

module random(
input clk,
output reg [6:0]s,
input [3:0] sw,
input [1:0] btn,
output reg [3:0] led
    );
reg [30:0] counter;
integer f;
always @ (posedge clk)
begin
if (counter==31'd500000000) begin
f=2;
if (f==2)
begin
s=7'b0100100;
end
 
counter<=0;
end
 
else begin 
 counter<=counter+1;
end
 
if (btn[0]==1) begin 
if (sw[0]*1+sw[1]*2+sw[2]*4+sw[3]*8==f)
begin 
led[0]=1;
end
 
else begin
led[3]=1;
end
 
end
end
end module
 
Error:

Here Both leds on Zybo  (led[0]and led [3) ]are Glowing just after programming device (i.e) before pressing button and switches....

I don't even understand why both LEDs are glowing even if one is in If and other is in Else.....Can anyone please help me with this...

Thanks in Advance......

 

 

 

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13 answers to this question

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@Aditya Gedela,

I'm not sure I can answer your question yet ... I'm looking at syntax errors in your code--for example, I can't seem to get the begins and ends to match together with the if properly.  For this reason, I'm not sure what your code does.  Can you post something to the forum that has the begins and ends lined up with the same indentation, and that places the block of the if indented further than the block before ... you know, standard indent rules?  It might help you figure out what's going on.

Second, I'm not sure what you are trying to do with "f".  You haven't given it a default value, you appear to only set it to 2, and it isn't a register but an integer.  From that description, a synthesizer might optimize it out of your code completely.  Is this what you want?

Dan

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Sample Code of what I intended to do:

module but(
input clk,
input [3:0]btn,
output reg [3:0]led
   );
always @(posedge clk) begin


    if (btn[0]==0) begin
       led[0]=1; 
    end


    if(btn[1]==1) begin
       led[1]=1;
    end


end
endmodule

 

Error :

 Both LEDS  (led0 and led1 on ZYBO) are high just after programming device without even pressing the buttons (btn0 and btn1).

Can anyone please help me with this?

Thanks in advance...........

 

 

 

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Hi!  Can you also post the active lines of the XDC file you are using?

Don't bother posting the comments :-) 

It should be something like...

set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];


set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }];
set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }];
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }];
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }];

set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }];
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }];
set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }];
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }];
 

based on https://github.com/Digilent/ZYBO/blob/master/Resources/XDC/ZYBO_Master.xdc

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Thanks for your replies,

Yeah, I programmed the device by uncommenting the lines required for LEDS ,buttons  and clk in the xdc file.... 

But the problem is both LEDS are becoming HIGH without even pressing the buttons on ZYBO...

According to my code, If btn[1] is pressed then only LED[1] should be HIGH, but it becomes HIGH as soon programming the device is finished.

Can anyone help me with this?

 

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Your code looks fine, so as far as I can guess you have two possible problems.

1) Your I/O pins are not connected as expected (e.g. you constraints are set wrong)

2) Your clock is not ticking

Humm... Maybe I have found it.

Have a look at page 21 of https://www.xilinx.com/support/documentation/university/XUP Boards/XUPZYBO/documentation/ZYBO_RM_B_V6.pdf

"Keep in mind that CLK125 will be disabled when the Ethernet PHY (IC1) is held in hardware reset by driving the PHYRSTB signal low."

You may also need to add the PHYRSTB signal to your design and drive it high, to bring the Ethernet PHY out of reset and start your 125MHz clock ticking.

Ouch - that is a trap for beginers

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@Aditya Gedela,

Sure.  Your problem is in your lack of initial statements.

Consider the difference between this

reg	ff;

always @(posedge clk)
	if (condition)
		ff <= 1'b1;

and this

reg	ff;

initial	ff = 1'b0;
always @(posedge clk)
	if (condition)
		ff <= 1'b1;

In the first case, the synthesizer will remove the condition and just set the flip flop to one--simply by assuming that since you haven't given it any initial condition, it might've been one to start out.  In the second case, the synthesizer will give you a warning about not being able to optimize your code properly, it will suggest you remove the initial statement, but ... it will do what you want.

That's what your code is missing: initial statements.

Dan

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Hi @D@n

I wrote initial statements but both my LEDS are glowing High at once as soon as I programmed the device even without pressing the button ..

My code:

module buttons(
input clk,
input [3:0] sw,
input [3:0] btn,
output reg [3:0] led 
    );
    initial led[0]=0;
    initial led[1]=0;
        
    always @(posedge clk) begin
    if(btn[0])
    begin
    led[0]=1;
    end
    else begin
    led[1]=1;
    end
    end
endmodule
Please help me out of this...

Thanks in advance..

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@Aditya Gedela,

But ... the XDC file you sent didn't have those lines uncommented.

My point: sometimes, Xilinx goes and assigns wires to things that aren't otherwise assigned.  You can usually discover this by looking through the logs and warnings.  As far as I can tell, your program above should've worked, though the "=" signs within the always statement are not what I would've used.  (I would used the "<=" statement in every always block--otherwise simulation and hardware might not match.)  That's why I'm looking for other causes to what you've seen.

Here, try this:

// Declare LED as wire's, not regs in your header ...
output	wire	[3:0]	led;

// That'll then allow you to do something like ...
assign led[3:0] = { (!btn[3]), (!btn[2]), (!btn[1]), btn[0] };

If all of your LED's light up, then you know you have a problem with your XDC file.  If three of the LED's light up, touch the button and see if another three LED's light up.  You can adjust the "!" signs above until you are confident that the right LED's are lighting for the right buttons.  Once that works, then go back and try your other program again.

Dan

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Hi @D@n

Yes it worked....

Basically what I need to do is when btn[0] is pressed then i should take the data from switches.

So I wrote the below code.

But whether my button is pressed are not, leds are getting assigned (they are glowing high if switch is high and low when switch is low)

 

module buttons(
input [3:0] sw,
input [3:0] btn,
output reg [3:0] led 
    );
      wire k;
    assign k = btn[0];
    always @(k) begin
    led[0]<=sw[0];
    led[1]<=sw[1];
    led[2]<=sw[2];
    led[3]<=sw[3];
    end
endmodule
Please help me out 

Thanks in advance.....

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@Aditya Gedela,

We may be on to this now ... I just noticed, what you are doing isn't legal Verilog.  On an always @(something), you are allowed to change things that depend upon that something.  But you've instead got always @(k), and nothing within it is depending upon k.  

The way to fix your code is to add the clock back in, as in,

module buttons(
input	clk,
input [3:0] sw,
input [3:0] btn,
output reg [3:0] led 
    );
      wire k;
    assign k = btn[0];
    always @(posedge clk) begin
    	if (btn[0])
        begin
          led[0]<=sw[0];
          led[1]<=sw[1];
          led[2]<=sw[2];
          led[3]<=sw[3];
		end
    end
endmodule

If you *really* want to do it without the clock, you'll need to create latches (unclocked memory) which is generally *bad*, so ... I'll just leave the code above as the way to solve your problem.

Dan

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