Using $urandom() function in vivado(ZYBO BOARD)

[Aditya Gedela]

I am using urandom() function to generate a random number. But while generating bitstream it is showing error in the implementation stage.

So,please help me with this.

 

Errors:

• [Place 30-494] The design is empty

• [Common 17-69] Command failed: Placer could not place all instances
•  

My code:

module random();
integer unsigned add;
initial
begin
repeat(5)
begin 
add=$urandom();
$display("address=%d",add);
end
end
endmodule

 

Thanks in advance......

[D@n]

@Aditya Gedela,

$urandom and $display are, to my knowledge, not synthesizable Verilog.  I would be surprised if Vivado allowed you to synthesize those for anything other than simulation purposes.

Dan

[jpeyron]

Hi @Aditya Gedela,

I googled and found some verilog code that might help with your needs here.

cheers,

Jon

[D@n]

@jpeyron, @Aditya Gedela,

LFSR's are wonderful.  I love using them.  They are useful for a great many things.  However, you may wish to be aware that an N-bit LFSR can be determined (state and taps) with only 2N output bits via nothing more than a set of simple linear equations.  Further, they work great when you want a series of (pretend) random bits, they aren't nearly as good when you want a random number, such as between 0 and 15.  Sure, you could grab 4-bits of an LFSR, but you tend to lose your randomness as you go about this.  So ... just be aware, they aren't really random: don't use them for cryptography.

If you are just trying to generate a somewhat random address, you might wish to use a bit-reversed counter.  It's not really random, but it might be random enough.  It'll also prevent whatever memory controller you are testing from optimizing sequential accesses ....

Dan

[Aditya Gedela]

Thanks for your replies,

I tried to  generate bitstream for the code which was posted (by @jpeyron)

But I got the same error (i.e) 

• [Place 30-494] The design is empty

• [Common 17-69] Command failed: Placer could not place all instances

Can you please help me out...

 

[Aditya Gedela]

@D@n

Can you please tell me about bit reversed counter which you mentioned in your post...

Thanks in Advance

[D@n]

@Aditya Gedela,

Let's see if I can reproduce it ... (I use it in this pwm project, and in the S6SoC that uses that):

reg	[(NBITS-1):0]	counter;
always @(posedge clk)
	counter <= counter + 1'b1;

wire [(NBITS-1):0]	address;
genvar	k;
generate for(k=0; k<NBITS; k=k+1)
begin : bit_reversal_loop
	assign address[k] = counter[(NBITS-1-k)];
end

That's how bit reversal works.  Now, for how random it is, consider a 3-bit sequence: 0, 1, 2, 3, 4, 5, 6, 7.  When bit reversed, it becomes: 0, 4, 2, 6, 1, 5, 3, 7.  It bounces back and forth between halves of the space: left half, right half, left half, right half, as opposed to bouncing between odd and even addresses.  The fun part of bit reversal is that it doesn't cost any logic to do.  The synthesizer just re-orders the wires and off you go.

Dan