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Vivado block diagram PmodOLEDrgb_axi_quad_spi_0_0


Question

I and 2 other partners are having problems with the PmodOLEDrgb block diagram. When it is in the IP flow pops up when the project is open, and below shows the list of errors. I think the Pmod has an error in it, which even when I open the block diagram.

When trying to regenerate the block diagram:

ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
endgroup

Opening the block diagram:

  • [BD 41-51] Could not find bus definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-51] Could not find bus definition for the interface: PmodOLEDrgb_out
  • [BD 41-49] Could not find abstraction definition for the interface: PmodOLEDrgb_out

When opening the packaged IP:

  • [IP_Flow 19-570] Bus Interface 'PmodOLEDrgb_out': Cannot find bus definition file for "digilentinc.com:interface:pmod:1.0"
  • [IP_Flow 19-569] Bus Interface 'PmodOLEDrgb_out': Cannot find bus abstraction file for "digilentinc.com:interface:pmod_rtl:1.0"

error vivado.PNG

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Hi @jocularjj,

What FPGA board are you using? Please take screen shots of the Vivado project with the block design included. Did you create another output clock(like 50mhz) to connect to the ext_spi_clk on the PmodOLEDrgb IP. What version of Vivado are you using? What OS? Did you have the vivado-library correctly added in the repository? Did you make sure to have board files installed? I went through adding the PmodOLEDrgb IP in vivado 2016.4 to a zynq core processor for the zybo with no issue and attached it below along with screen shots.

PmodOLEDrgb.zip

pmodOLEDrgb_screen_shots.zip

Edited by jpeyron
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1 hour ago, jpeyron said:

Hi @jocularjj,

What FPGA board are you using? Please take screen shots of the Vivado project with the block design included. Did you create another output clock(like 50mhz) to connect to the ext_spi_clk on the PmodOLEDrgb IP. What version of Vivado are you using? What OS? Did you have the vivado-library correctly added in the repository? Did you make sure to have board files installed? I went through adding the PmodOLEDrgb IP in vivado 2016.4 to a zynq core processor for the zybo with no issue and attached it below along with screen shots.

PmodOLEDrgb.zip

pmodOLEDrgb_screen_shots.zip

Thanks for the quick reply I am using Nexsys DDR board

Block diagram is attached.

Clk3 from ip wiz which is 50 Mhz is attached to ext_spi_clk

AXI aclk  and axi aclk2 is 100 Mhz from the clock wizard also.

I am using 2016.2 and have more problems when I tried 2016.4 of vivado, and Win 8.1. I do have the board updated in the vivado directory and I am pointing to the ip repo in ip catalog. 

block diagram.PNG

also I am getting errors that don't let me attach the ports from the two blocks to be external, I attached a new image to show my method for connecting in addition to control t and right click make external, and trying to drag the ports.

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WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports PmodOLEDrgb_out'
ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.

Connect board component.png

Edited by jocularjj
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Hi @jocularjj,

Could you hit Regenerate layout and take a screen shot of the whole block diagram. Have you installed the board files? When adding the Pmod IP's are you right clicking on the port on the board selection and then choosing the pmod you want from the selection as shown below? It appears that you have not connected either Pmod IP to a port(JA,JB....) in the block design you attached.  Have you gone through the Getting started with Microblaze tutorial here. Also it looks like you have the PmodBT2 IP in the block diagram? I am attaching both a project made in Vivado 2016.2(project_4) and in Vivado 2016.4(PmodOLEDrgb_nexys4_ddr) with both the PmodOLEDrgb and PmodBT2 in each of the projects. The error posted below is only in Vivado 2016.4 and you can disregard these. They are just saying that the IP cores were make with a different board.

PmodOLEDrgb_nexys4_ddr.zip

project_4.zip

PmodOLEDgrb_6.jpg

PmodOLEDgrb_5.jpg

PmodOLEDgrb_7.jpg

Edited by jpeyron
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Yes board files are in image.

Yes I have used the right click method on ports in board file and added that way.

Yes I generated this base through a microserver tutorial on digilinc.

I will try the block diagrams. thanks for letting me look at them.

whole block diagram.PNGopening the files it looks like the pmodOLEDrgb I pulled from the from digilent are a newer version than yours. after updating the drivers it looks like I am still getting critical warnings and Jb or JC falls off of PMOD OLEDrgb. I can update pictures tomorrow.

Edited by jocularjj
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The Port still doesn't appear on the oledrgb output port isn't working with the downloaded files in 2016.2 or 2016.4 with either file.

Showing Board file and IP catelog and pmod

your oled driver is in ip catalog, only using the digilien ip lib and generic lib, so no conflict.PNG

Missing port connectors

port still disappears.PNG

Missing output port doesn't add in any of the ways described in the previous posts(You can see that the output pmod is on the bt mod not the oled)

2016.2 output port still not showing up on the pmod oledrgb, board is seen.PNG

 

loosing port occurs on both 2016 2 and 2016 4.PNG

In the other 2016.4 the project is not able to compile like 2016.2. The port doesn't connect to the oledrgb output port either. When selecting the add there is no known valid portions of the oled display. I am starting to think it is a problem with the board file even though I am getting oled driver errors.pmod oled adding output port.PNG

loosing port occurs on both 2016 2 and 2016 4.PNG

 

 

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I have multiple drivers that are hanging around in the IP report although there are only one in my block diagram.

multiple pmod oledrgb.PNG

Here is the OLEDrgb error message from the OLEDrgb driver that was attached earlier to this thread.

oledrgb locked.PNG

Edited by jocularjj
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Hi @jocularjj,

Looking at one of your more recent screen shots which i attached below. You need to first disconnect the board component that is not being used by right clicking on the Pmod port connector JC under boards and selecting the disconnect board component. Then left click on the Pmod port you want the PmodOLEDrgb to connect to and drag it to the Pmod port out of the Pmod IP. I have included screen shots below.

cheers,

Jon

PmodOLEDgrb_8.jpg

PmodOLEDgrb_9.jpg

PmodOLEDgrb_10.jpg

PmodOLEDgrb_11.jpg

PmodOLEDgrb_12.jpg

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when I try that I get a list of error messages below.error messages.PNG

  • [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
  • [BD 41-51] Could not find bus definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-51] Could not find bus definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:pmod_rtl:1.0
  • [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:pmod_rtl:1.0', cannot be found. Interface port: 'jc' cannot be created
  • [BD 41-51] Could not find bus definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-51] Could not find bus definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out

 

 

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to my knowledge I am pointing to the IP from diligent . To the left is the pointer in my IP catalog to D:\IP\ to the right I have D:\IP\pmods with the list of pmods that are givenip picture.PNG

Adding the whole file to the repository doesn't seem to help either :(

master library.PNG

  • [BD 41-51] Could not find bus definition for the interface: PmodOLEDrgb_out
  • [BD 41-49] Could not find abstraction definition for the interface: PmodOLEDrgb_out
  • [BD 41-51] Could not find bus definition for the interface: Pmod_out
  • [BD 41-49] Could not find abstraction definition for the interface: Pmod_out
  • [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:pmod_rtl:1.0
  • [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:pmod_rtl:1.0', cannot be found. Interface port: 'jb' cannot be created
  • [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:pmod_rtl:1.0
  • [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:pmod_rtl:1.0', cannot be found. Interface port: 'jc' cannot be created
  • [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:pmod_rtl:1.0
  • [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:pmod_rtl:1.0', cannot be found. Interface port: 'jb' cannot be created
  • [BD 41-52] Could not find the abstraction definition specified by the vlnv: digilentinc.com:interface:pmod_rtl:1.0
  • [BD 41-181] Type specified by the VLNV: 'digilentinc.com:interface:pmod_rtl:1.0', cannot be found. Interface port: 'jc' cannot be created

No item to connect while IP repo as suggested is open to see and board is setup.

connector JC board component cannot be connected because no possible options to connect.PNG

 

Edited by jocularjj
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Hi @jocularjj,

Some of the Pmod IP's also need the files in the if  folder as well as the files in the ip fold to work correctly. You either include in the ip repository manager the full folder that you download to get the IP's from github called vivado-library-master when downloaded or add the if folder to what you have already added in the repository manager. This should fix the errors that you are getting.

cheers,

Jon

PmodOLEDgrb_16.jpg

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