Nexys4ddr SRAM to DDR Test Problem

[Shaw]

Hello,

I am using Xilinx Vivado 2014.3.1

I'd like to use SRAM to DDR Component in my project. First of all, I want to test the component, the top module is at the bottom.

Just like the top module, I write the ddr three times at three address, and read them after some cycles. However, the read data in board is wrong and random.

The  result is here:

		ram_dq_i	ram_dq_o
1st write	1234		0000
2nd write	5678		0000
3rd write	9abc		0000
1st read	1111		1234
2nd read	2222		5678
3rd read	3333		9abc

However, the read data(ram_dq_o) may be change with cycles.

Could someone help me with this issue?

Thanks

test_ddr.v

[jpeyron]

Hi @Shaw,

I found a thread that deals with SRAM to DDR here. I believe the dead github link in the thread should be point here. Hope this helps!

cheers,

Jon

[D@n]

@Shaw,

Looking over your code, I'd be concerned that you aren't accommodating the clock frequency changes internal to the core. 

Try this for me: make every SRAM interaction have a couple steps.  Step 1) With CEN=1, set up all of your parameters.  Hold there for at least two clocks at 100MHz (perhaps more?  I'm not sure how this timing is supposed to work ...).  Step 2) set CEN to zero.  Step 3) Set CEN to one without changing anything else.  Hold for at least two clocks.  Step 4) Set up your next transaction, leaving CEN equal to one.  Hold the new transaction for at least two clocks.  Step 5) Drop CEN--changing nothing else.  Step 6) Raise CEN again--changing nothing else for two clocks, etc.

The big difference between this approach and the code you've presented is that it splits your idle state(s) up into two: one where you hold the data elements from the last transaction, and one new substate where you set up the elements for the next.

Let me know how that works for you,

Dan