PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

[paolo_unice]

Hi everyone;

I'm a beginner with FPGA. I have a Zedboard xc7z020-clg484-1 and two converters PmodDA2, PmodAD1. Do you have a working VHDL code to interface these devices with the board?

Thank you!

[jpeyron]

Hi @paolo_unice,

To test the PmodAD1 i used a power supply and a waveform generator to test the analog input. For the PmodDA2 is used an o-scope to test the analog output.

cheers,

Jon

[Notarobot]

D@n and @jpeyron

Personally I like ongoing technical discussion and find it useful. However, since no requirements were specified it might be missing the point.

If the ADC sampling rate is low (below 100kHz or so) even single CPU can do everything. I believe that the main intent of Xilinx creating Vivado and putting hard cores on FPGA is to employ high level programming and minimize HDL which is almost impossible to maintain for large projects.

Thank you all!

[D@n]

@jpeyron and @paolo_unice,

Are we making this problem harder than it is?  Why not just create a simple FIFO in block RAM, make it into a piece of AXI IP--could even be AXI lite if you wante, and have the ARM read from it and dump it into the DDR3 memory?  Further, while I'm not an expert on interrupts for the ARM, if you created an interrupt and an interrupt controller for it, you could then have complete control over where the values were written to memory, how many values were written, how long they were written for, etc.  If you wanted to get one stop more complicated, you could even connect this to a DMA controller on the ARM and then have the ARM automatically move the data around for you.

I mean ... the reality is that the second part of his task requires a CPU, so why not engage the CPU on the first part of the task?

Dan

[jpeyron]

@D@n and @paolo_unice,

@D@n is 100% correct. I forgot that the DDR3 is tied to the PS with all of our FPGA's that have an ARM on them like the Zedboard and Zybo.  This makes this task much more difficult. Here is a thread that talks about this situation on the Avnet forums as well. My last suggestion on my previous post on this thread might be easier to set up then. The project I attached in the linked thread has the Zynq processor with the PmodAD1 connected to the axi gpio already done and connected using the add block feature. All you would need to do is add the VHDL/Verilog code for the PmodDA2 that you already have and add it to the design in a similar way. You would need to use SDK as well. The Project also has the SDK code for the PmodAD1 so you would have something to refer to as well as the getting started with zynq tutorial here.

cheers,

Jon

[D@n]

@jpeyron,

Thanks for the mention, but ... I didn't think you could do for the ZedBoard what I did for the Arty or I would've proposed the idea.  Unlike the Arty which doesn't have an ARM, the ARM on the ZedBoard also needs access to that memory--hence my controller would need to be modified into more of an arbiter than a controller. 

Were this my project, I would do the following:

• Build a FIFO that would read from the controller every time a new sample was available
• Build a controller for the other side of that FIFO that could sit on your system bus.  It would have a couple of control registers, such as

1. What memory did you wish to send this data to
2. How much data did you wish to capture
3. How much data had been captured already.

• You can find one such controller that I've written, albeit for a wishbone bus and not an AXI bus here.  One of the things my controller allows is the idea of bursting data.  Hence you might wish to wait until your FIFO was half full before bursting half the FIFO's buffer out.  This will help to minimize your impact on the memory channel.
• If you chose to use a wishbone bus like I did, you'd then need a wishbone to AXI converter since the ZedBoard and ARM are using an AXI bus.
• Then, you need to connect the ARM AXI memory channel to your data AXI memory channel via some form of arbiter.  You can find an example of a wishbone arbiter here, but ... I don't have one for AXI.  The fact that AXI has five channels of communication to it just ... complicates things.

 

So, while I'd love to offer the pieces of a solution, I really don't have all the pieces you'd need.  Were it on any other FPGA only board, I'd be there already 'cause you wouldn't need the AXI interface. 

Dan

[jpeyron]

Hi @paolo_unice,

Here is a thread about using the DDR3 without a MIG(pretty complicated). Here is a xilinx PDF that deals with Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions. A less complicated solution using VHDL/Verilog would be to use the MIG IP like @D@n discusses in this thread. Another potential way to accomplish this is to use the Zynq processor with IP cores. Here is a thread that talks about doing this with the PmodAD1 using the VHDL/Verilog solutions for the Pmods and a new feature in Vivado 2016.x called add block.

cheers,

Jon

[paolo_unice]

Ok; I received the information.

And, if I want to save in the DDR3 memory the information received from the PmodAD1, and after read this information for PmodDA2; what can I do? What is the way to follow?

I'm sorry but I started working with FPGA 10 days ago and I have a lot of doubts.

Thank you for your patience!

[Notarobot]

Paolo,

In addition to all said I would suggest to take datasheets for both AD1 and DA2 chips and try determine what you should expect when connect them. If you calculate how much time it takes for each conversion you will see that the what is usable voltage and frequency ranges for the DA. Also draw the circuit diagram.

While the AD7476 conversion time is constant for a given clock, the time of conversion for DA is clock and input code dependent.

 

[D@n]

@paolo_unice,

Is it possible?  Yes.

Is it worth doing?  Probably, depends upon your application.  For example, you might be able to place a nice digital amplifier, filter, or even an echo generator in the middle.

Is it hard?  That depends: are the two devices running at different clock rates?  If so, then it's ... not nearly as simple.  If not, then things are easy.

The basics of it is this: On every valid sample, you need to create and keep track of a sample_valid flag, and then you'll want to gate *all* of your signal processing with that sample_valid flag.  This will allow you to do signal processing with a sample waveform that is slower than your clock rate.  Then, at the end, you can use the gate to output your value, or (gasp!) even get sloppy and just trust that the output will be there on the top of every sample.  This only works, though, if the two are sampled at the same rate.

For anything beyond that, I'd need to stare at the code involved.

Dan

[paolo_unice]

Thank you @Notarobot @D@n @jpeyron!

The programs are working for PmodDA2 and PmodAD1. I understand the fact about the I/O constraints and now I want to test the two communications togheter. So, I connect the two Pmod qt the board. How can I program the board with the two VHDL codes for DA2 and AD1? Is it possible? What can I do?

[Notarobot]

@Paolo,

The purpose of I/O constraints is only to connect internal signals to the particular pins of the IC. These signals should be specified in your design and match accepted designation.

You can verify your code by checking the clock signal on the Pmod pin with the oscilloscope. If you scope can't show 100 MHz you can add divider vhdl block temporarily.

Hope this help!

P.S. Try to find "ActivePowerMeter" project on Digilent web site. It contains both AD1 and DA2 vhdl examples.

[paolo_unice]

Is it correct if I set this in I/O constraints?

set_property PACKAGE_PIN Y9 [get_ports CLK]

So, I say to the input port CLK to take the signal from the pin Y9 (100Mhz clock of the board). Is it correct?

Thank you; Paolo.

[paolo_unice]

I did everything; I programmed the board and now what can I do to test if the program effectively work on the board? I want just to see if the PINs related to D1 and D2 gives the correct response. How can I send a test input to the Zedboard? 

[D@n]

@paolo_unice,

I try to keep my designs very simple: using only one clock.  In such a design, the only time constraint you need is the one on the clock that (should) come with the master XDC file.  You will need to manage (personally) any timing between the FPGA and external interfaces, but ... the one constraint in your XDC file is still usually sufficient. 

Where things start getting dicey is when you have multiple clocks and you need to transition between them, or when you wish to tell Xilinx/Vivado about the constraints between the FPGA and any external interfaces.  I have yet to need to learn how to do any of this and I've been working with FPGA's for many years.

Dan

[paolo_unice]

3 hours ago, D@n said:

@paolo_unice,

Sorry, just noticed you were adapting a Nexys2 design to the ZedBoard, not that you were using a Nexys 2 board.  Sorry.

Unlike the Nexys 2, the ZedBoard requires Vivado, and Vivado uses XDC files.  You'll want lines in your XDC file looking something like:

set_property PACKAGE_PIN H1 [get_ports SYNCn]
set_property IOSTANDARD LVCMOS33 [get_ports SYNCn]
set_property PACKAGE_PIN K2 [get_ports DIN1]
set_property IOSTANDARD LVCMOS33 [get_ports DIN1]
set_property PACKAGE_PIN H2 [get_ports DIN2]
set_property IOSTANDARD LVCMOS33 [get_ports DIN2]
set_property PACKAGE_PIN G3 [get_ports SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports SCLK]

These particular pin numbers, though, were copied from an XDC file for my basys board, so they are almost certainly wrong for  the ZedBoard.  You'll want to copy from the ZedBoard XDC file, linked from the ZedBoard resource center found here.  Look through that file for examples of how to do things, it should make ... some sense (perhaps not much) ... even to a beginner.  Make your first couple passes through the project test passes--outputting values as I referenced above--until you and your voltmeter have verified that you have the pin out properly.  Then move forward with connecting the actual PModDA2 to your board.

Dan

Thank you @D@n! Now I understand.

Can you tell me something about time constraints? When and why I have to define them?

 

[D@n]

@paolo_unice,

Sorry, just noticed you were adapting a Nexys2 design to the ZedBoard, not that you were using a Nexys 2 board.  Sorry.

Unlike the Nexys 2, the ZedBoard requires Vivado, and Vivado uses XDC files.  You'll want lines in your XDC file looking something like:

set_property PACKAGE_PIN H1 [get_ports SYNCn]
set_property IOSTANDARD LVCMOS33 [get_ports SYNCn]
set_property PACKAGE_PIN K2 [get_ports DIN1]
set_property IOSTANDARD LVCMOS33 [get_ports DIN1]
set_property PACKAGE_PIN H2 [get_ports DIN2]
set_property IOSTANDARD LVCMOS33 [get_ports DIN2]
set_property PACKAGE_PIN G3 [get_ports SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports SCLK]

These particular pin numbers, though, were copied from an XDC file for my basys board, so they are almost certainly wrong for  the ZedBoard.  You'll want to copy from the ZedBoard XDC file, linked from the ZedBoard resource center found here.  Look through that file for examples of how to do things, it should make ... some sense (perhaps not much) ... even to a beginner.  Make your first couple passes through the project test passes--outputting values as I referenced above--until you and your voltmeter have verified that you have the pin out properly.  Then move forward with connecting the actual PModDA2 to your board.

Dan

[paolo_unice]

6 minutes ago, D@n said:

If you are using the Nexys2 board,

I use Zedboard xc7z020-clg484-1. And Vivado. It is not correct to use that file for this board?

I'm sorry but I'm really a beginner and I don't understand a lot about it.

[D@n]

@paolo_unice,

If you are using the Nexys2 board, you'll want to be working with Xilinx's ISE, not Vivado.  ISE uses UCF files to contain it's constraints.  You can find the UCF file you need to start from here, on the resource page for the Nexys 2.  There are two UCF files linked there (bottom right hand of the screen), depending upon which Nexys2 board you are using.

Inside your UCF file, you'll need something like ...

##JA
NET "SYNCn"      LOC = "L15" | IOSTANDARD=LVCMOS33;
NET "DIN1"       LOC = "K12" | IOSTANDARD=LVCMOS33;
NET "DIN2"       LOC = "L17" | IOSTANDARD=LVCMOS33;
NET "SCLK"       LOC = "M15" | IOSTANDARD=LVCMOS33;

Do double check the pin numbers, though, against how you have chosen to lay out your board.  For example, you might have the PMod on another PMod port, on the top (or bottom) of this port, and I might have the wires in the reverse order ... but you should get the idea from here.  If you've never done this before, it's often worthwhile setting up the pins as outputs and outputting a constant value to them--something you can double check with a voltmeter to make certain you have the pin assignment right.  You can then re-adjust the DIN1 and DIN2 lines to be inputs within your VHDL code--once you know you have them assigned properly.

Dan

[paolo_unice]

Thank you for the answers.

I found the code for PmodDA2 (in attach) for Nexys2. I just modified the DivFactor (2 instead of 3). You think that is it good?

I have to set some I/O constraints in Vivado in order to select the output port to connect the Pmod? Can you explain me something about it please?

 

Thank you. Paolo

DA2RefComp.vhd

[Notarobot]

Hi paolo_unice,

I would suggest to look at the Digilent publication "PmodAD2 & PmodDA1 Demo". The web page also contains VHDL code for this demo.

DA1 piece of this code I tested successfully. Pmod AD1 requires different VHDL driver. Working code was published on this forum by the user Hamster. His original code was created for the limited range and you might need to check whether it still obtains 12 bits.

Have fun!

 

 

[jpeyron]

Hi @paolo_unice,

Here is VHDL code for the PmodAD1. The resources page for the PmodDA1 is here. @D@n covered information about the PmodDA2. 

cheers,

Jon

[D@n]

@paolo_unice,

You can find an example of how to use the PModDA2 on its resource page (along with other examples).  You can also find a similar resource page for the PModAD2, with such examples as this one linked from it.

Hope these links help,

Dan