HS2 HS3 Slew rates

[wrb123]

Hi,

We are designing a board that will have many ultrascale FPGA's on it and will use the HS1, HS2, and/or HS3.in series config.

What is output slew rate on the JTAG CLK so I can determine termination requirements?

What is the maximum number of xilinx ultrascale FPGA loads do you recommend before buffering any of the JTAG lines? For CLK termination, I'd probably just use 50 Ohm thevinen termination depending on your slew rate.

 

[JColvin]

Hello @wrb123,

I have asked one of our senior engineers about this; I hope to have a response back to you in the next day or so.

Thanks,
JColvin

[jpeyron]

Hi @wrb123,

I'm posting to let you know we have not forgot about your question and are still working on getting you this information.

cheers,

Jon

[sbobrowicz]

I'd recommend you use the JTAG HS3 and put a 14-pin connector on your board.

I'll reach out to you over the forum messenger with some additional information about the HS3 that should help you make the needed calculations.