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nisarg_shah114

artix nexys 4 and keyboard

Question

I want to interface keyboard with artix 7 nexys 4 fpga board....which keyboard can we interface that is usb or ps/2 keyboards ....if both please tell me how. also can we program fpga for ps/2 keybpard and interface with usb pin using ps2 to usb converter....??? 

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Hello @nisarg_shah114,

The Nexys 4 has an onboard USB host connector with a microcontroller that sits between it and the FPGA. The microcontroller will handle the USB HID protocol and emultates PS/2 bus signals. There will be no need for an external PS/2 to USB converter at all. This section of the Nexys 4 reference manual has details regarding the keyboard connection. The section before it gives details to the HID controller.

 

I hope this information helps you. Do not hesitate to ask any questions you may have, and I will do what I can to help.

AndrewHolzer

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On 3/13/2017 at 10:02 PM, AndrewHolzer said:

Hello @nisarg_shah114,

The Nexys 4 has an onboard USB host connector with a microcontroller that sits between it and the FPGA. The microcontroller will handle the USB HID protocol and emultates PS/2 bus signals. There will be no need for an external PS/2 to USB converter at all. This section of the Nexys 4 reference manual has details regarding the keyboard connection. The section before it gives details to the HID controller.

 

I hope this information helps you. Do not hesitate to ask any questions you may have, and I will do what I can to help.

AndrewHolzer

thanks a lot sir.......this has been a great help.....one more thing i would like to ask you regarding the vhdl code for the interfacing.... i have attached 2 file which contains code.. one  is main code "keyboard" and other is sub module "keyboard_top" using port maping, now can  u please check if the code is appropriate or not as in the second code name "keyboard_top"in the third line use work.ps2_compnents.all; vivado is showing error...please help me out as i am a self learner and its very difficult to get information ...Thanks again for help..:) 

keyboard.txt

keyboard_top.txt

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Hi @nisarg_shah114,

Could you please send a quote of the Vivado error or a screenshot of it? Without seeing the error I would guess that you need an equivalent library statement to make the library that your custom package resides in visible. If that is the case when you get back to me, I will give you the details on how to create your own library using the Vivado tools.

Looking forward to hearing back from you,

AndrewHolzer

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@nisarg_shah114,

Looking over your code, I'm not sure what error Vivado is giving you ... but it also looks like you are missing several pieces of the PS/2 protocol.  For example, the clock and data lines are bi-directional.  Inside my top level, to handle this bidirectionality, I have (in my Verilog code) the two lines:

assign io_ps2_clk = (!o_ps2_clk)?1'b0:1'bz;
assign io_ps2_dat = (!o_ps2_dat)?1'b0:1'bz;

If you are not interested in writing to the PS2 port (as I needed to do to get the mouse working), I suppose you might not need these lines, allowing instead the two port lines to be complete inputs.

However, in my XDC file, I declare that each of these pins has a pull up on the line.   Without that pull up, it is possible that the slave might wait forever for the clock line to go high--making all of your communication impossible.

Further, looking at your shift register implementation, I would *highly* discourage you from looking for clock events on anything but clock lines.  I think you will find some very difficult timing problems going that road.  Indeed, I would suggest that, within your designs, you use as few clocks as possible, and that *every* switch from one clock domain (positive edge of one clock) to another (positive edge of another clock, or even negative edge of the first) be very carefully engineered to avoid any metastability issues.

Just some thoughts,

Dan

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17 hours ago, AndrewHolzer said:

Hi @nisarg_shah114,

Could you please send a quote of the Vivado error or a screenshot of it? Without seeing the error I would guess that you need an equivalent library statement to make the library that your custom package resides in visible. If that is the case when you get back to me, I will give you the details on how to create your own library using the Vivado tools.

Looking forward to hearing back from you,

AndrewHolzer

actually found this code from one of the pdf available on the net....the first code is perfectly giving the elaborated design but after adding source and adding second file that is "keyboard_top" i am getting the following error.... here are the screen shot of the error....please tell me the changes i need to make in the code to interface the keyboard

Capture1.JPG

Capture2.JPG

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5 minutes ago, nisarg_shah114 said:

actually found this code from one of the pdf available on the net....the first code is perfectly giving the elaborated design but after adding source and adding second file that is "keyboard_top" i am getting the following error.... here are the screen shot of the error....please tell me the changes i need to make in the code to interface the keyboard

Capture1.JPG

Capture2.JPG

 

111111.JPG

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13 hours ago, D@n said:

@nisarg_shah114,

Looking over your code, I'm not sure what error Vivado is giving you ... but it also looks like you are missing several pieces of the PS/2 protocol.  For example, the clock and data lines are bi-directional.  Inside my top level, to handle this bidirectionality, I have (in my Verilog code) the two lines:


assign io_ps2_clk = (!o_ps2_clk)?1'b0:1'bz;
assign io_ps2_dat = (!o_ps2_dat)?1'b0:1'bz;

If you are not interested in writing to the PS2 port (as I needed to do to get the mouse working), I suppose you might not need these lines, allowing instead the two port lines to be complete inputs.

However, in my XDC file, I declare that each of these pins has a pull up on the line.   Without that pull up, it is possible that the slave might wait forever for the clock line to go high--making all of your communication impossible.

Further, looking at your shift register implementation, I would *highly* discourage you from looking for clock events on anything but clock lines.  I think you will find some very difficult timing problems going that road.  Indeed, I would suggest that, within your designs, you use as few clocks as possible, and that *every* switch from one clock domain (positive edge of one clock) to another (positive edge of another clock, or even negative edge of the first) be very carefully engineered to avoid any metastability issues.

Just some thoughts,

Dan

thanks a lot for taking out time and going through it..actually sir, i am very new to fpga and vhdl so i found this code on net to learn interfacing...now the first code attached above is working appropriately giving elaborated design.....but when I add source and port map the second code the following errors are obtained...here i have attached the snapshot of the error....i also searched verilog code online but was not able to find it or compile it....however it would be great help if code go through these errors and guide me how should i make changes in the code....Thanx a lot again...

111111.JPG

Capture1.JPG

Capture2.JPG

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