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xl07

NetFPGA problem

Question

HI, does anybody know how to debug NetFPGA, because I find that it spends me 15 minutes to compile the verilog hdl code, once there is a problem, I have to check the verilog hdl source code of NetFPGA in project/reference_switch/src/ manually and recompile the verilog hdl codes. 

 

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Just now, D@n said:

@xl07,

Can you tell me at all anything more about what you are struggling with?  What's working and what's not?

Dan

Sorry, the question is the following. In output_queues module, there are 8 queues, 0,2,4,6 queues are used for mac interface while 1,3,5,7 queues are used for cpu queues. In switch project, I want to add 4 additional queues as input queues for mac interface. And I find the 1,3,5,7 queues of output_queues module are not used in switch project, so I use these 1,3,5,7 queues as input queues. I changed the code of remove_pkt.v to get packets from 0,2,4,6 queues of output queues instead of from 0,1,2,3,4,5,6,7 output queues. When a packet of in_data_0 go into user_data_path its destination_port will be changed as 1, and in_data_2 packet will be 3 destination port, and so on, so that input_queues can put these packets into 1,3,5,7 queues.

All the codes are compiled successfully, but the NetFPGA switch does not transport any packet, and I find debugging this problem is so hard. Any advice is very welcomed.  

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@xl07,

According to the "known issues", "The HW test does not provide sufficient indications to understand what went wrong and why, e.g. which packet had an error, type of error etc."  Sounds like this is just what you've discovered.

Would you like to try to develop a solution to deal with the issue?

Dan

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On 2017/3/11 at 10:57 PM, D@n said:

@xl07,

According to the "known issues", "The HW test does not provide sufficient indications to understand what went wrong and why, e.g. which packet had an error, type of error etc."  Sounds like this is just what you've discovered.

Would you like to try to develop a solution to deal with the issue?

Dan

Thanks, Dan. I would like to find bugs by checking related registers step by step. Although this is slow, but it will look out the root of problem.

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