HI, does anybody know how to debug NetFPGA, because I find that it spends me 15 minutes to compile the verilog hdl code, once there is a problem, I have to check the verilog hdl source code of NetFPGA in project/reference_switch/src/ manually and recompile the verilog hdl codes.
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xl07
HI, does anybody know how to debug NetFPGA, because I find that it spends me 15 minutes to compile the verilog hdl code, once there is a problem, I have to check the verilog hdl source code of NetFPGA in project/reference_switch/src/ manually and recompile the verilog hdl codes.
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