• 0
imagepix

LVCMOS18 on ARTY 7 evaluation board

Question

 am using the ARTY 7 evaluation board from digilent which used the Artix-7 x35AT cpg324 packaging. Using one of the general purpose I/O banks i want to configure it for 1.8V configuration. (I am using this for 3-wire SPI to generate the spi clock and read the output from my ADC which are at 1.8V)

I looked through the documentation to configure this on the board and after going through all the relevant documents i am still unable to configure the I/O to LVCMOS18 standard.

Here is the table which mentions how to configure the files

enter image description here

And here is how i have configured in the XDC file

set_property IOSTANDARD LVCMOS18 [get_ports adc_conv_oc]
set_property IOSTANDARD LVCMOS18 [get_ports adc_din]
set_property IOSTANDARD LVCMOS18 [get_ports adc_sclk]

set_property PACKAGE_PIN V15 [get_ports adc_conv_oc]
set_property PACKAGE_PIN U16 [get_ports adc_din]
set_property PACKAGE_PIN T11 [get_ports adc_sclk]

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

The synthesized design has the following I/O port which indicates that the I?O's are configured for LVCMOS18 on bank 14 and VCC = 1.8V

enter image description here

The UG470 documentation mentions the following:

The 7 series FPGAs have two I/O bank types: high-range (HR I/O) banks support 3.3V,2.5V, and a few lower voltage I/O standards, and high-performance (HP I/O) banks support I/O standards of 1.8V or lower voltage. The dedicated configuration and JTAG I/O are located in bank 0. Bank 0 is a high-range bank type on all devices except for the Virtex-7 HT devices. Several of the configuration modes also rely on pins in bank 14 and/or bank 15. Bank 14 and bank 15 are HR I/O banks in the Spartan-7, Artix-7 and Kintex-7 families, but are always HP I/O banks in the Virtex-7 family. See UG475, 7 seriesFPGAs Packaging and Pinout Guide for bank information for each device. Note: The CFGBVS pin is not available on Virtex-7 HT devices. Virtex-7 HT devices support only 1.8V operation for configuration banks. The CFGBVS pin setting determines the I/O voltage support for bank 0 at all times, and for bank 14 and bank 15 during configuration. The VCCO supply for each configuration bankmust match the CFGBVS selection if used during configuration — 2.5V or 3.3V if CFGBVS is tied to VCCO_0, and 1.8V or 1.5V if CFGBVS is tied to GND.

but somehow i always get the output to be 3.3V. Any ideas on how to solve this? Does the Arty-7 evaluation board for some reason not allow me to configure the voltages to LVCMOS18?

Thanks

Share this post


Link to post
Share on other sites

2 answers to this question

Recommended Posts

  • 0

Hi @imagepix,

Unfortunately the Arty output voltage on the I/O pins are not configurable. Its output  is only 3.3v. If you have to output 1.8v and are using the Arty then you need to use a level shifter like our PmodLVlshft here. The Zedboard, Nexys Video and Genesys 2 here have FMC's on them that you can adjust the voltage to 1.8v.

thank you,

Jon

Share this post


Link to post
Share on other sites
  • 0

Thanks for the answer jpeyron. 

Hopefully in a future iteration they provide the option of changing the I/O voltage of at least one bank. Just provides more flexibility to the user.

Thanks

 

Share this post


Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now