combinatorial logic loop on Basys3 board

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My UART receiver utilizes a finite state machine to keep track of the receive data and its protocol, including start bit, 8-bit data, and stop bit. When I compiled it in vivado, it created an error message : combinatorial logic loop. I guess it did not like the state variable tracking the data as it goes from state to state in a circular manner. The resolution is to change it, but if it is understood, I could simply declare it in the *.xdc file as "set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>". I tried that but it did not recognize the command net_nets. It said the command is not supported in the xdc constraint file. Why? Is it because I got the student discount version or something else? By the way what is <myHier/myNet>? The name of the variable that created the issue?

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You get out of combinatorial loops by insisting that logic transition on the positive edge of a clock.  Any thing transitioning on a clock will break a loop.  Otherwise, if you have a variable, we'll call it A (perhaps it's your state variable), that depends upon the last value of A--but without a clock in between--you will get a logic loop.  In general, a logic loop means things are broken--put the clock back in and it should fix it.


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