Nexys4ddr SRAM to DDR Component Problem

[Shaw]

Hello,

I am using Xilinx Vivado 2014.3.1

I'd like to use SRAM to DDR Component in my project. But I am newbie in VHDL, so I could just use the methods from this post.

And finally, I had made a testbench which could write data into DDR memory and read data from the DDR. It's successful in Synthesis, Implementation and Generate bitstream. There are no critical wornings and errors.

I want to use 7-segment to display the data that read from the DDR, however, it didn't work.

This is my top module.

Could someone help me with this issue?

Thanks,

Shaw

test_ddr.v

[D@n]

@Shaw,

I took a long look at your code, and the biggest problem I saw was the clock transition issue.  The SRAM-DDR controller is only given a 200MHz clock, yet your code is running at a different clock speed (or so I'm presuming--I have no idea what your clock function is doing).  So ... may I suggest that you need to disable the cen line (raise it to one) between your memory commands?

Dan

[Shaw]

13 hours ago, D@n said:

@Shaw,

I took a long look at your code, and the biggest problem I saw was the clock transition issue.  The SRAM-DDR controller is only given a 200MHz clock, yet your code is running at a different clock speed (or so I'm presuming--I have no idea what your clock function is doing).  So ... may I suggest that you need to disable the cen line (raise it to one) between your memory commands?

Dan

Thank you Dan for fast response.

I'm sorry about my unclear description. My project has two clock, the first one is system clock(100MHZ), the second is DDR clock(200MHZ). The clock function is used to generate the two clock.

And then, I used your suggestion and disabled the cen line between the memory commands. Fortunately, when I saw the 7-segment, the result is right.

Now, I'd like to use SRAM to DDR Component in another bigger project. At that, I want to kown the reason why I should disable the cen line.

Thanks,

Shaw

[D@n]

@Shaw,

You mean .... I made a guess and got it right?  COOL!!! 

So .... here's what I thought might be going on: 1) transistors don't change instantaneously.  They require some set up time, and a time period where everything holds constant.  2) Wire's wander through your design in such a way that they arrive at their destination with varying delays.  As long as these delays are before the setup and hold time before the next clock, no one cares.  In your case, they were crossing clock domains, so ... you couldn't guarantee that all the wires in your SRAM setup were arriving at the next clock in time.  Some might be arriving early, some late.  For this reason, I counseled you to 3) turn off the CE line before changing any of the wires, and then not to turn the CE line back on until they were changed.  That way 4) the SRAM component would only ever see lines that had already made the clock domain crossing properly.

At least .... that was my reason.  Not knowing what was actually going on made my advice more of an educated guess than anything else.

Dan

 

[Shaw]

Thank you for the explanation. This indeed helps a lot as it brings my thinking on the right track.

Shaw