ZYBO Board w/ XADC

[Squirrel]

I was wondering if anyone had experience with the ZYBO board getting the XADC interface to work properly. I have the following diagram in Vivado 2014.4:

 

<Vivado2014_4_Diagram.JPG>

 

The associated XADC wizard settings are as follows:

 

<XADC_Wizard1.JPG>

 

<XADC_Wizard2.JPG>

 

This lets me get the temperature from the XADC, but I am getting 'weird' values for XADC pairs 0-3 (which are hardwired to the XADC PMOD connector on the ZYBO); there doesn't appear to be a dependence on temperature though... here is AUX0, for example:

 

<TempVsAUX0.JPG>

 

In relation to VpVn (VpVn - AUXn) I observe for all 4 AUX channels:

 

<WpWn_Minus_AUX.JPG>

 

I'm not quite sure why AUX1 always agrees with VpVn, especially because they are sampled at different places in the C code...

 

My source is as follows (null checks, comments, etc. removed for brevity):

 

<XADC_Source.JPG>

 

So, a few questions...

 

1) What is going on with the above? Anyone have any thoughts?

2) I didn't set up anything in the constraints (XDC) file for the XADC pins because I believe they are hardwired (and I get critical warnings when I do)... is this correct?

3) Are these the only four XADC inputs possible for the ZYBO (N/P pairs)? The wiring diagram seems to indicate this is the case... if it is, does anyone have a suggestion for an external ADC? Something well documented would be preferred.

[sLowe]

Hey Squirrel,

 

To get the XADC working properly on the Artix-7 boards which use the same XADC, I had to declare them in the .xdc. If you can locate the xadc block in the synthesized schematic, you can see for sure if they actually are. Below is what my schematic looks like,

 

 

This was my code for the basys3 xdc

#Pmod Header JXADC
#Sch name = XA1_P
set_property PACKAGE_PIN J3 [get_ports {vauxp6}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxp6}]
#Sch name = XA2_P
set_property PACKAGE_PIN L3 [get_ports {vauxp14}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxp14}]
#Sch name = XA3_P
set_property PACKAGE_PIN M2 [get_ports {vauxp7}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxp7}]
#Sch name = XA4_P
set_property PACKAGE_PIN N2 [get_ports {vauxp15}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxp15}]
#Sch name = XA1_N
set_property PACKAGE_PIN K3 [get_ports {vauxn6}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxn6}]
#Sch name = XA2_N
set_property PACKAGE_PIN M3 [get_ports {vauxn14}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxn14}]
#Sch name = XA3_N
set_property PACKAGE_PIN M1 [get_ports {vauxn7}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxn7}]
#Sch name = XA4_N
set_property PACKAGE_PIN N1 [get_ports {vauxn15}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {vauxn15}]

 

 

 

I also had to name the ports in the xadc as vauxn6, vauxp6 etc. It looks like although the reference manual has aux1,2,3,4. The actual XADC ports are different. In the picture below is the FPGA bank for the ZYBO where the aux inputs connect.

 

 

So 1 -> 14

     2 -> 7

     3 -> 15

     4 -> 6

 

Within your xadc wizard select these ports instead of 1,2,3,4. For an example of some working Verilog you can find a project here. https://reference.digilentinc.com/nexys4-ddr:xadcdemo

 

I believe you only get these 4 inputs with the ZYBO.

 

Hope this helps and Ill keep my eye on this stream if there is anything else I forgot about. Also this may not answer all your questions because I am not very familiar with microblaze projects.

 

-Sam Lowe

[Squirrel]

This has gotten me significantly farther, thank you for the reply!

 

For anyone who browses this topic later:

The XAdcPs_RawToVoltage conversion macro is 3.0 V based and not 1.0 V; create your own for the AUX channels (unless anyone knows of one already there?)