How to modify Zybo Master.xdc to use inbuilt clok?

[Nilakshan]

##Clock signal
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports clk_50]
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];

In this constraints what modifications should I used to get 50MHz clock?

[artvvb]

@Nilakshan

The following XDC code may or may not work

#Clock Signal
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS33} [get_ports clk_50]
create_clock -add -name sys_clk_pin -period 20.00 -waveform {0 10} [get_ports clk_50]

You need to use the create_clock line to define the frequency of the clock, where the period and waveform parameters take values in nanoseconds.

The more normal way to create a slower clock is to use Vivado's Clocking Wizard IP core to use the clocking hardware (MMCMs and PLLs) on the Zybo - I am unsure if Vivado interprets the period and waveform changes so as to use this hardware.

Hope this helps,

Arthur

[jamey.hicks]

Isn't that the clock source that is used by the Zynq internal PLL's? If so, it is used to produce the 4 fclks that are available directly to the PL (programmable logic). The frequency of each fclk is controlled by control registers that can be modified from a device driver.