shashi Posted March 4, 2017 Share Posted March 4, 2017 HI there, I have a zed board. Developing a design in HLS for algorithmic acceleration. When I run the c-simulation for my design in HLS , it is not run showing the following error: But when i do c-synthesis it synthesizes the design with synthesis report, where in under latency and interval I see question marks: '?' why this happens and how do i understand this behavior? How can i get it corrected? Thaks in advance Link to comment Share on other sites More sharing options...
shashi Posted March 4, 2017 Author Share Posted March 4, 2017 Sorry this is for zed board: Link to comment Share on other sites More sharing options...
D@n Posted March 4, 2017 Share Posted March 4, 2017 @shashi, It might help if you posted the whole error from the Vivado HLS console, not the 20 lines that followed the error. As for the latency and interval numbers ... my guess is that they remain "?" because Vivado never got that far--it stopped short after an earlier error. Dan Link to comment Share on other sites More sharing options...
shashi Posted March 4, 2017 Author Share Posted March 4, 2017 Hi Dan, Thanks for the reply. I have attached here the entire design files and the error log to give you a good perspective of my problem. Can you please look into them and give me your feedback.? It would be a great help to me. Thanks in advance HLS_files.zip Link to comment Share on other sites More sharing options...
D@n Posted March 4, 2017 Share Posted March 4, 2017 @shashi, Sorry ... I'm not seeing it. Perhaps someone else on the forum might be able to figure out what's going on, or you may need to post on Xilinx's HLS forum. Dan Link to comment Share on other sites More sharing options...
JColvin Posted March 10, 2017 Share Posted March 10, 2017 Hi @shashi, I don't really know much about HLS, but I did a quick search and it looks like it has something to do with Variable Bound Loops as per this Xilinx forum thread and this Xilinx Answer Record. I don't know what Variable Bound Loops are, but I found the user guide for Vivado 2016.2 HLS (which it looks like you're using) that talks about them on page 314 here, which looks like the analog for what the Xilinx employee referred their customer to. Thanks, JColvin Link to comment Share on other sites More sharing options...
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shashi
HI there,
I have a zed board. Developing a design in HLS for algorithmic acceleration.
When I run the c-simulation for my design in HLS , it is not run showing the following error:
But when i do c-synthesis it synthesizes the design with synthesis report, where in under latency and interval I see question marks: '?'
why this happens and how do i understand this behavior? How can i get it corrected?
Thaks in advance
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