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shashi

HLS design synthesized but not run in c simulation for zed board

Question

HI there,

I have a zed board. Developing a design in HLS for algorithmic acceleration. 

When I run the c-simulation for my design in HLS , it is not run showing the following error:

But when i do c-synthesis it synthesizes the design with synthesis report, where in under latency and interval I see question marks: '?'

why this happens and how do i understand this behavior? How can i get it corrected?

 

Thaks in advance

synth_report.PNG

err.PNG

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5 answers to this question

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@shashi,

It might help if you posted the whole error from the Vivado HLS console, not the 20 lines that followed the error.

As for the latency and interval numbers ... my guess is that they remain "?" because Vivado never got that far--it stopped short after an earlier error.

Dan

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Hi Dan,

Thanks for the reply. I have attached here the entire design files and the error log to give you a good perspective of my problem.

Can you please look into them and give me your feedback.? It would be a great help to me.

Thanks in advance

 

 

HLS_files.zip

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Hi @shashi,

I don't really know much about HLS, but I did a quick search and it looks like it has something to do with Variable Bound Loops as per this Xilinx forum thread and this Xilinx Answer Record. I don't know what Variable Bound Loops are, but I found the user guide for Vivado 2016.2 HLS (which it looks like you're using) that talks about them on page 314 here, which looks like the analog for what the Xilinx employee referred their customer to.

Thanks,
JColvin

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