B SULLY

Tutorial Suggestion/Question

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I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial:

"After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper."

Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear. 

  • Copy generated wrapper to allow user edits
  • Let VIvado manage wrapper and auto-update

The window also states;"You can either add or copy the HDL wrapper file to the project. Use copy option if you would like to modify this file."

The next step moves on to generate a bitstream file so I'm going to assume that this file will not be edited any longer. I wish the tutorial would provide a bit more context to the steps laid out and how the operations used in this simple project would/could be used in another project. So far I appears that once I'm done this this tutorial I will only have learned how to accomplish the same task, only with a bit more confidence.

After step 6 I am given another window the tutorial does not make any mention of. The window is titled Launch Runs with text; "Launch the selected synthesis or implementation runs." and provides 3 choices.

  • Launch runs on local host:
  • Generate scrips only
  • Number of jobs [2] {with option to change value}

There is also a choice of Launch directory.

On this one I'm totally clueless. I realize that Diligent is not responsible  for changes in the Vivado IDE but I as a company focused on education I think it could do better on updating tutorials to accurately reflect the changes in Vivado. I would also LOVE to see more Zybo tutorials, they are far and few between on the net. The book is alright but a bit difficult to navigate to topics the relevant for beginners.

If anyone could respond with instruction on how I SHOULD have proceed with these options and what any of these options really mean I would appreciate it, as I have now come across some warnings in the TCL console about needing a "AXI BFM license to run".

 

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Hi @B Sully,

Thank you for your feedback on the Getting started with Zynq tutorial. We are in the process of updating our demos and tutorials to Vivado 2016.4. For your first question, we choose Let Vivado manage wrapper and auto-update and leave all the other setting alone. For your second part with the three different choices. As of right now we are leaving it with the default selections except the number of job and that is a preference based on how many of your cores do you want dedicated to the process of synthesis/implementation or generate bitstream. I believe the Launch runs on local host would allow you to dictate where the processing takes place. I believe the Generate scrips only gives you more choices on how it runs implementation/synthesis or generate bitstream.  Also here is a xilinx forum thread that talks about the AXI BFM license. Hope this helps!

cheers,

Jon

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jpeyron,

Thanks for the reply and link. I have run into more options not discussed in the tutorial can you recommend an appropriate place to post? After generating a bitstream leaving the default options I am asked to choose from:

  • Open Implementation Design
  • view reports
  • open hardware manager
  • generate memory config file

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@B Sully,

I have linked this forum thread for our suggestions from customers, so posting here is the best way to make suggestions.  These choices depend on what your project does and what you want to see. If you want to see the implementation design ,reports, generate a memory config file or open up the hardware manager. You can just close this popup with out choosing anything as well. Here is a xilinx pdf for using vivado 2016.4 as well. These tutorials Here and here might be helpful as well.

cheers,

Jon

Edited by jpeyron

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Thanks,

Would you have any idea about when the updated tutorial can be expected?

I would love to see a tutorial just about using 3rd party IPs for the Zync/Vivado environment like from OpenCores and the like. Since the Zync device is not a normal FPGA it has been a bit hard to translate tutorials written for the vanilla FPGAs.

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Hi @B Sully,

Unfortunately, I would not be able to give an ETA on when an updated version will be available. Also I have refered your request to the appropriate people. 

cheers,

Jon

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