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c simulation error in HLS


Hi there,

I get this error when I run the C simulation in HLS to implement on zed board. I know that this error occurs when  classes or class member functions are set as the top-level for synthesis.

But i am not able to figure out where exactly i am going wrong. Can someone guide me here.? 



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Gosh, HLS?  Ouch.  I am by no means an expert on HLS.  You might wish to turn around and ask your question in the Xilinx forums instead.  My own personal experience with HLS is only counseling people who've been let down by it.

That said, I do see some problems with your HLS synthesis that might be part of what you are struggling with.  I figure these are problems simply because, were I the HLS program, I would struggle with these.

For one, and to my knowledge, HLS doesn't give you access to the DDR3 SDRAM.  Sorry.  I know you've been asking about it, and I guess I just didn't realize the task you were trying to accomplish.  Those big huge arrays you have?  HLS would implement those in on-chip block RAM, a very limited resource.  Anything connected to SDRAM needs to be connected to an AXI4 bus, and it will only ever be able to read so many values at once--never more than 64-128 bits IIRC depending upon the size of your DDR3 SDRAM data width.

And double precision floating point math?  Ok, sure, the FPGA can do it, but ... that's gonna cost you.  Whether or not HLS can do it, well, that's a different question--and a good one for the Xilinx forums.  I do know that while an FPGA can do floating point math, it will cost several clock cycles to do.  I'm not sure how well HLS can handle something that will cross multiple clock cycles.

Are you trying to build an interpolator to display an image or some such in real user timer?  While it sounds like a fun idea, and a very good use of an FPGA, it's not an easy task to accomplish.  Were I to build such an interpolator, I wouldn't go beyond doing a single set of inputs at any given time with HLS--although I'm not sure how I would adjust HLS to only use 6 inputs at a time.

Gosh ... I might even want to do a bi-quadratic interpolator (it sounds like a fun challenge!), and send the results either to a VGA-type display or to display memory.  Now that would be a fun challenge of a problem, but I would never start that problem with HLS.  I just wouldn't trust HLS to handle the difficult parts of the problem properly.  I'd probably try to push back against the floating point requirement, to see if I couldn't do it in fixed point--floating point is just *really* hard.  It's not that it cannot be done, just that ... it's hard.

Hope that helps,


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Thanks for your reply. I have a Virtex 7 board too. Maybe i will try to implement on that if it is going to take a lot of BRAM.

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