Question

Hello

I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. 

If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice.

Thanks in advance!

=============================================================================================

    ///////////////////////////////////////////////////////////////////
    //XADC Instantiation
    //////////////////////////////////////////////////////////////////
    
    xadc_wiz_0  XLXI_7 (
        .daddr_in    (Address_in), 
        .dclk_in     (clk), 
        .den_in      (enable & |sw), 
        .di_in       (0),
        .dwe_in      (0),
        .busy_out    (),
        .vauxp15     (xa_p[2]),
        .vauxn15     (xa_n[2]),
        .vauxp14     (xa_p[0]),
        .vauxn14     (xa_n[0]),               
        .vauxp7      (xa_p[1]),
        .vauxn7      (xa_n[1]),
        .vauxp6      (xa_p[3]),
        .vauxn6      (xa_n[3]),               
        .do_out      (data),
        .vp_in       (vp_in),
        .vn_in       (vn_in),
        .eoc_out     (enable),
        .channel_out (channel_out),
        .drdy_out    (ready)
    );

=============================================================================================

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@macellan,

If you take a peek at the Xilinx 7-series libraries guide, somewhere around page 440 you'll find both the description of the XADC as well as an example of how to instantiate it into your own design.  They offer both Verilog as well as VHDL examples on how to instantiate the hardware.

You might manage to figure out the "dot type coding" by looking at it, as there is a direct VHDL analog, but here's the basics: .A(v) is used when there is a parameter or input/output wire to the core named A and you want connect your local value v to that input/output/(generic) parameter.  The location you presented above is not the parameter/generics section, though, but rather the input/output wire passing section.  Further, in the example Xilinx gives in their guide, the parameter section in verilog starts with #( and ends with ).  If I understand VHDL well enough, that's equivalent to your generic section.

Hope this helps,

Dan

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Thank you for the answers both are very helpful. Let me make some more trials and reading then some more questions may appear...

macellan

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I did some more reading during the weekend but somethings are not clear yet ...

Sometime ago I've prepared a slow clock counter using clocking wizard and there I've instantiated the clock core as a component which works without any problem. There is no instantiation in the top level file. Instead when I click on "+" sign next to clock ip figure in the sources tab there is an instantiation inside it. But I didn't do anything there. So what is difference here??

p.s ZYBO example design link

https://github.com/Digilent/Zybo-XADC

Thanks in advance! 

 

TL_Counter.vhd

Untitled.png

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Hi guys,

I am trying to understand the implementation of the XADC, are there any example project done in VHDL for the XADC implementation and reading out data from the registers?

 

 

Thanks in advance.

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HI @jpeyron,

 

Here is the brief scenario of my problem , I am trying to use the the XADC for some data acquisition task, so I am trying to configure the XADC so that I can read the analog input that I provide with a signal generator. from the XADC document I read the EOC gives HIGH when there is a conversion available and then (I use DRP interfacing) then the DEN must go HIGH at the next clock cycle, in the following cycle the DADDR is captured and the DRDY goes high in the previous clock cycle when the data is available is ready to be read at DO. so using the same logic I have implemented this to see the working. 

image.png.f51322abce5023a2f2aee8bcd78e4776.png

image.thumb.png.aa4c4fb90f8e97a25415e1f92cfe61d6.png

So no errors when I synthesis the work. I have used the SETUP DEBUG option and implemented the ILA block for the logic analysis and to see the output.

 

My processor is using 40MHz clock and the global clock for the operation of ila block is the same.  and I see  the output like this

image.png.0e13c2ee2cbd70454e0a8a00085208af.png

image.png.34f8be910c4fd9f42c63ef9153327a8a.png

 

I am trying to know if this is implemented correct because I provide a 121KHz input of 1.0V peak to peak with offset of 0.5V dc and I get a triangular kind of wave output. Thought The voltage level is kind of matching with the input level. The task i will be using this FPGA is for analyzing the analog waveform, based that data acquisition. 

 

Thanks in advance.

Masterblock.vhd

Edited by Newbiee
mistakes

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@Newbiee,

Your FPGA clock speed is 40MHz, your incoming signal is at 121kHz, what is the sample rate of the signal produced by the XADC?  If  it is anywhere near 250kHz, then the output you are seeing is to be expected.

Dan

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Hi @D@n,

 

Thank you for the answer, I am sharing this pic to clarify more on the topic of clock. I am using the FCLK from the processor to the XADC dclk and that is 40MHz. So the the sampling rate is dependent on the ADCclk which is lesser than the dclk is what I understand from the documetation of XADC. 

image.thumb.png.75a8311d8a29bf4f516ff3bebc32f01a.png

so my question

1) the time or clock sequence on the ila debugger is based on the same lock too? if not can you give more info, please. 

2) is my output still correct? 

please help me.

thank you in advance.

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