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silverwolfman

Question regarding to cmod s6 module

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Hello,

I am using the cmod s6 eval board as the reference for my prototype board.  I wonder how many board layers do I need if I am going to use the same package like the cmod s6 package XC6SLX 4-2CPG196 does?   

In additon, when I use the iMPACT to reprogram the chip flash, it took me 12 min for burn the code in the flash, is there any suggestion I could speed up this process? 

Thanks,

Edited by silverwolfman

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@silverwolfman,

I don't have my S6 on my desk to tell you how much time it took me to load the flash, but I do know I didn't use iMPACT.  You can find my work here.  In particular, the flash loader is called zipload, and depends upon the using the Digilent Adept utilities to load an initial configuration (generated from this toplevel file) into the flash.

Dan

P.S. I'll be redoing my work again soon, to prove that the updated ZipCPU can still fit (and work) on the device.  You can see some of my update works in the 8-bit branch of the s6soc project, but ... although it builds, it hasn't been tested yet so ... it's still a work in progress.

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17 hours ago, D@n said:

@silverwolfman,

I don't have my S6 on my desk to tell you how much time it took me to load the flash, but I do know I didn't use iMPACT.  You can find my work here.  In particular, the flash loader is called zipload, and depends upon the using the Digilent Adept utilities to load an initial configuration (generated from this toplevel file) into the flash.

Dan

P.S. I'll be redoing my work again soon, to prove that the updated ZipCPU can still fit (and work) on the device.  You can see some of my update works in the 8-bit branch of the s6soc project, but ... although it builds, it hasn't been tested yet so ... it's still a work in progress.

Thank you so much for the information, Dan.

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@silverwolfman,

So ... I timed how long it took to write a configuration to the flash today and it took just less than 3 minutes (2:45).  The configuration, however, took up less than 1/16th of the flash space (despite using almost all of the FPGA's resources).  I might've been able to speed that up by about a factor of two if I just erased every sector rather than trying to read every sector first to determine if it needed erasing.  Using those numbers, it might take as long as 22mins to rewrite the entire flash.

Just a thought,

Dan

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