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Image processing on Zybo


Nilakshan

Question

I'm doing a project in which I'm trying to implement image processing algorithms.I a novice to zybo.I need answers for some questions

1.How to load a hex file to zybo?

2.Is there any issue using UART(J11) port(means any voltage issue)

3.Will zybo supports external clocking?

Thanks in advance

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Since the Zybo has that dual-core ARM SOC in the Zynq FPGA I would assume that you are using either a Linux variant OS or RTOS port and doing your image processing in the PS. How you get your raw data to either the PL or ARM cores depends to some degree on your OS. The Zybo is a nice cheap way to experiment with Zynq but is a bit IO challenged. The best interface might be the Ethernet port.

I don't understand your question about the UART as it's a USB UART connected to the ARM SOC. Of course you can always connect any two pins of one of the PMOD connectors to an HDL UART in your PL. This would require using a TTL UART-USB cable or adapter. FTDI and Adafruit provide these.

Not sure what you mean by "external clocking". The Zybo doesn't offer an external clock input to the PL except for the 125 MHz Ethernet PHY reference clock and this clock isn't running when the PHY reset is asserted.

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The schematic that Digilent provides isn't really complete so I'm "reading between the lines" of what little information is provided. The reference to the 3.3V-1.8V voltage translation has to do with the MIO Bank 501 voltage and is simply there to make the FT2232H UART pins electrically compatible with the SOC IO pin requirements. This really has no impact on how you use J11 as it can only be used as a USB device. To be honest,I'm not wasting my time to research the details.

Did you plan on using J11 as something other than a USB serial port? The FT2232H device connected to J11 is also the sole JTAG endpoint so you don't want to destroy it. I realize that perhaps your choice of hardware platform is not up to you but my guess is that the Zybo isn't the appropriate one for your application... unless this is a classroom exercise.

I know that it's a drag but even though such boards as the Zybo are sold as a development tool for anyone unless the user has a fair competency in HDL/FPGA development, the ability to read schematics, and some competency in electronics the actual usability of these boards is quite limited. Unfortunately, there is a lot of stuff out there that seems like a good development platform for almost any application but in practice is only useful for replicating a limited variation of the vendors demo code. By carefully limiting details about the product companies take money from customers who wouldn't buy their products if they understood the limitations.

The Zybo is, for the money,  a fine platform for learning about embedded Linux or RTOS OSes, Xilinx Zynq development tools, and even connecting PL IP to an ARM core. It's not, in my opinion, a great general purpose development platform.

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Hi Nilakshan,

Could you be more specific about how you are trying to accomplish your image processing project.   Are you using embedded linux, RTOS or are you trying to do this in hdl? Knowing how you are trying to accomplish your project will help us with how to load the hex file. J11 is part of our proprietarty programming solution so unfortunately i wouldn't be able to assist with you with trying to use it other then its intended purpose.  I talked to our layout engineer and he said you would be able to bring in an external clock in on Pmod Port D on the differentially paired JD3 PN pins. Could you be more specific about the which voltage values (3.3V > 1.8 V) you couldn't understand?

cheers,

Jon

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Yes JD3_P could be used as an external clock input and I'd suggest grounding the JD3_N pin to minimize noise. This is because the traces from the PMOD are routed differentially and may not (hopefully not ) be spaced far apart from each other to be electromagnetically de-coupled. In selecting a connector pin to use as a clock input don't go by the signal names at the connector.... go by the FPGA IO bank pin names the signal connects to; though they should match as far as the "_P" or "_N" designators go. You want an FPGA IO bank pin with "_P" in the name... but the pin has to be able to be connected to a global clock network so FPGA pins with "SRCC", "MRCC" in the pin designator name are OK. If you're going to make your own interfaces you should be familiar with Xilinx's naming convention. The previous statements assume that you want to use a single-ended clock source. If you have a clock source with differential outputs then there may be other things to consider depending on the IO_STANDARD like pull-up resistors which ideally would be as close to the FPGA PN pair pins as possible. You would then use the appropriate pair as JD3_P and JD3_N to receive your clock. The problem is then would be to maintain proper differential and impedance characteristics between the PMOD and your clock source pins.

Be aware that the differential PMOD pins don't have a current limiting resistor. Also, pay attention to the IO_STANDARD signal restrictions that the pin is given in your constraints file. You need to minimize over-shoot and under-shoot so how the clock source is connected is important. And, of course, the output characteristics of your clock source has to be compatible with the FPGA pin IO_STANDARD. Usually, when someone wants to use a specific external clock to drive the PL logic they have a data interface in mind. It's not clear from your questions what it is that you want to do... except "load a hex file" and do something with that USB UART.... you're not making it easy to provide useful guidance.

 

 

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