Need code for Ethernet for spartan 6

[srikanth]

I need the code for Ethernet Interface. Does anybody in this group provide the code? It would be appreciated. Thank you

[zygot]

srikanth,

Hi, I need code for a product that will make me rich.... wanna swap code?

But seriously, what exactly is it that you want to do? What hardware platform are you using? "code for Ethernet" is a pretty nebulous phrase that touches on a very wide range of topics.

If, say your board is the Atlys, and all you want to do is send and receive Ethernet packets between two boards over an Ethernet cable you don't need any "code"... just an understanding of how the PHY works and some fundamental HDL skills can accomplish that. There's some hints on how to proceed buried within the Project Vault. Have you looked in places like Open Cores? There are a lot of ways to do almost anything that you might want to do and a bit of research and work might be a place to start.

[D@n]

@srikanth,

@zygot is right.  The code depends upon what hardware you are using.  Are you using an MII interface?  RMII?  or trying to build the PHY yourself?  You can find code on OpenCores for just about all of the above, but knowing what hardware you are using would help me point you towards something more valuable.

Dan

[srikanth]

Thanks guys for your reply. I need the code for Anvyl Spartan-6 FPGA using VHDL. 

 

[D@n]

@srikanth,

Have you looked into the Anvyl demo test suite at all?  It uses an AXI ethernet lite controller, so if you are looking for a working out of the box solution that would work with microblaze, then you just found it.

There is an OpenCores ethernet controller using the MII interface.  That's close to RMII, although it might be overkill for what you need.  It works off of the wishbone bus interface, although it is in Verilog.

Another wishbone option, this one B4/pipelined, would be to check out the RMII code I've got for the Arty, and associated MDIO code ... with the exception that it is also in Verilog and not VHDL.  RMII is a standard, so it shouldn't be specific to your board, as is Verilog and the Arty code only uses one Xilinx specific feature (* ASYNC_REG *) which you can adjust as needed to whatever else you might use it for.  The files depend upon others within the directory, but this should get you a touch closer.  Sadly, while the verilog code for this interface works, the demo/example control software code (or from the PC/host here) ... still needs to be touched up.

Dan

 

[D@n]

@srikanth,

Almost forgot: @hamster put together an open source Ethernet driver for the Arty  that is in VHDL.  You might find that more usable than the links above,

Dan

[zygot]

The Anvyl board uses the LAN8720 10/100 PHY. In general an MII interface has 8-bit RxTx SDR data ports that can be connected to a MAC ( soft for the Spartan 6 as I recall ) or FPGA logic if you don't need a full-fledged MAC. The LAN8720 only presents 2 bits of Tx/Rx data but at 4X BYTE data rate in SDR mode. So  2 data bits at 50 MHz gives you the 100 Mbps maximum Ethernet speed with RMII where 8 bits at 12.5 MHz in MII would accomplish the same data rate. For Gigabit Ehternet PHYs RMII usually uses DDR and half the data bits which complicates timing considerations for non-MAC designs. The good news is that you don't have to worry about DDR. The bad news is that if you use the MicroBlaze approach that I suspect Digilent provides with their demo code ( I've never used this board ) then you will need a soft MAC IP. Xilinx will give you a temporary license for their "Lite" version for evaluation purposes or you'll have to find one from another source. (Of course you could write your own, but I figure that if you could do that you wouldn't be asking your question ). The other problem with this approach is that the whole MicroBlaze infrastructure uses a lot of FPGA resources that you might want for other things. So your first question is this: do you need a MAC for your application?

You might find the approach taken by Jon Dawson with his CHIPS 2.0 approach to FPGA design an interesting alternative. Look up the TCP_SOCKET project on OpenCores. He has code available on Github but curiously the Ethernet example is missing from that resource. There are alternatives available from various sources but you may have to kiss a lot of frogs to find your dream ( sorry, can't think of a gender-neutral title to replace prince/princess ). It really does matter what it is that you need to do with your Ethernet interface and you have chosen to keep that a mystery. If you look around most of the FPGA vendors offer demo code to help with their development boards.

This is just my opinion but if an FPGA board vendor includes an Ethernet PHY on a product then they should also provide HDL that doesn't require a license so that their customers can use that product as expected from reading the datasheet. Digilent seems to think that pushing customers toward Xilinx IP is a free pass even when the IP isn't free. This is a disappointment to me and I suspect a lot of customers.

[D@n]

@zygot, is this the open cores tcp-socket page you are referencing?

The specification for the ethernet chip was quite fascinating.  Your right, it is a two-bit interface.  I'd gotten used to the four bit interface.

Dan

 

[amkichu]

On 2/26/2017 at 1:55 PM, D@n said:

It uses an AXI ethernet lite controller

Dear @D@n

I successfully established this AXI ethernet lite connection. I need to establish TCP connection between the MicroBlaze (socket server) and Matlab (socket client) to pass some settings data from a variable, say a=0x53, in Matlab to MicroBlaze which pass the value to a GPIO. 

Is it possible?

[D@n]

@amkichu,

My guess is that you are asking the wrong question.  Yes, it is possible.  However, having never used microblaze, I can't really tell you how to do it.  I know I have code lying around here somewhere which can create an input I/O port for Octave which can be used for a purpose similar to this, but ... you may need to do some coding to get there.

Dan