DSP48E1 25x18 2's compliment multiplier type

[ysogreen]

For a piece of research I am looking to conduct, I am wanting to compare the efficiency of hardware multipliers with different types of designed multipliers. As I have a NEXYS4 DDR, I am looking to use the 25x18 multiplier on board as a basis for comparison. Is there any reference as to what the hardware design is for the on-board multiplier so I have a better frame of reference of what I am comparing to (i.e. is it a Wallace tree multiplier?).

--RG

[D@n]

@ysogreen,

Have you looked at the documentation for the DSP48E1 slice used within the Nexys-4?  Sadly, looking through it, I can't figure out how they built that multiplier--maybe I'm missing they key details, but that's where I'd look for it.  If you can't find it there, see if you can look into Xilinx's older documents.  Sometimes you can find a companies presentation of their work--before they lock it up as proprietary. 

If you've got the opportunity, I would love to offer you some of my own Verilog multiply work to evaluate.  Interested?  I have a couple of implementations of a 32x32 to 64 bit multiply, and here (used within a CPU), as well as some code to generate a generic NxN bit multiply--both somewhat optimized for use within an FPGA.  Let me know if you are interested,

Dan