Fklein23

Addition of 2 bits

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I am puzzled by this code, which is mentioned in problem 2.7 of the Roth, John and Lee book, "Digital Systems Design Using Verilog". Both the signals are single bits.

When I have simulated this code, it agrees with the instructor's manual. Both a simulation and the manual say that if A has a value of 1,  B<=A+1 results in B = 1.

Now I can understand {carry, sum} = A + 1; should result in {1,0}. But if the LHS is also a single bit, why is B=1 the result????? Why isn't the result 0?

 

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Hi Fklein23,

We do not have the book "Digital Systems Design Using Verilog". Could you post the code that you are working with?

cheers,

Jon

Edited by jpeyron

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