Basys3 Board Config File Question

[Woody Arnold]

The Basys3 board configuration .xdc file has:

create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK]

Question:  Is this 100Mhz  clock already on the board or does this command create the clock in the Xilinx FPGA?

Thanks !

Woody Arnold

[D@n]

@Woody Arnold,

If you look at page 5 of the Basys3 schematic, in cell D1-D2, you can see a 100MHz clock chip feeding into the FPGA.  That's the 100MHz clock that gets described within the XDC file you are looking at.

Dan

[Woody Arnold]

On 2/18/2017 at 0:01 PM, D@n said:

@Woody Arnold,

Thank-you Dan !

I haven't found it yet on the schematic but will find it.  I appreciate your reply.

Woody

 

If you look at page 5 of the Basys3 schematic, in cell D1-D2, you can see a 100MHz clock chip feeding into the FPGA.  That's the 100MHz clock that gets described within the XDC file you are looking at.

Dan