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Nexys Video FT2232H Disable JTAG During Use

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I'm using the Nexys Video board and I'd like to use the FIFO capability of the FTDI chip (IC13 connected to J12) to get data from the FPGA quickly and easily while keeping the JTAG lines high-impedance. I would like to use the FT2232H FIFO port while using our own JTAG (J17). The JTAG lines on that chip are high impedance until the USB cable is plugged in and I'd like to keep them high impedance while using the USB port. If you don't know, can you send me the schematic page for IC13/J12?

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Hi swift,

Unfortunately, our programming solution is proprietary. That is why there is a black page in the schematic. I would not be able to assist you with this. Maybe one of the communicy members on the forum would be able to futher assist you.

thank you,

Jon

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I don't think the answer to swift's question has to infringe on the proprietary nature of Digilent's programming solution. I think he poses a legitimate use case that the board ought to support.

We are in a similar situation where we want to use the USB FIFO functionality but we need to use a different JTAG driver. We want to hold the JTAG lines on the FTDI device at high-impedance while we use the DPTI functionality.

Jon, are you saying that it can't be done, (i.e. Digilent's proprietary sauce makes it impossible to hold the JTAG lines at high-impedance with the USB port plugged in), or might there be a software driver work around to this issue? Is it possible to programmatically disconnect the JTAG port?

Any help you can give us on this matter would be of great use. I have spent the last hour and half digging through the Adept 2 SDK and trying a few things out, but to no avail...

Thank you,

--Andrew

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Hi @andremwkeller,

It should be in high impedance whenever the JTAG port isn’t enabled. Are you trying to access the FIFO directly or are using DPTI? If you are trying to access the FIFO mode directly then make sure that you either tri-state BDBUS7 or drive it low, which will disable the JTAG tri-state buffers and allow for the JTAG signals to be driven from J17. If you are using DPTI we will look further into process for DPTI for you.

thank you,

Jon

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@jpeyron,

Thank you for your reply. I spent most of my efforts using DPTI. I am working off of the DPTI-demo on the Nexys Video Board. By access the FIFO directly, do you mean using the FTDI drivers provided by FTDI for the FT2232HQ IC used for FIFO/JTAG channels to the board? If that is a possibility, it is definitely something worth exploring. Is that the best course of action you recommend for a direct FIFO access approach?

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Hi @andremwkeller,

I had reached out to our design engineer and they responded that they will have to investigate this because they expect the JTAG bus to be tri-stated when not enabled and it shouldn’t be enabled while the DPTI port is enabled. It could be possible that the Xilinx tools will try to enable the jtag port if you use auto connect, which could be what’s causing the problem. Are you wanting to use a separate JTAG module so that you can debug via JTAG while using DPTI at the same time. They are pretty confident we had this working here at one point. In any case they will have to look at this next week. 

thank you,

Jon

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Hi @andremwkeller,

I received a response form our design engineer and is as follows "I looked at this a bit more and DPTI (asynchronous and synchronous) ports are functioning correctly. Enabling either type of port does not result in the JTAG tri-state buffers on the Nexys Video being inadvertently enabled. I was able to simultaneously loop the JTAG IDCODE of the FPGA using a JtagHS2 plugged into J17 while at the same time performing a synchronous DPTI transfer between the FPGA Logic and PC. This leads me to believe that the issue is actually related to hardware manager in Vivado. To confirm my suspicion I tried opening hardware manager (without auto connect) with both the NexysVideo and JTAGHS2 connected. As expected hardware manager found two JTAG devices, with the NexysVideo being the first device in the list. The NexysVideo showed the correct IDCODE (and FPGA) but the HS2 shows that there is no target (and no JTAG devices) in the chain. I used an oscilloscope to probe the JTGEN signal (which enables the tri-state buffers of the Nexys Video’s onboard JTAG programming circuit) and found that when Vivado Hardware Manager generates the list of cables it keeps the JTAG port enabled indefinitely even after populating the list. This in turn is preventing the HS2 from being able to control the scan chain because there is a drive conflict. The onboard programmer is able to continue to manipulate the scan chain because there are series resistors between J17 and the onboard bus and the onboard buffers directly drive the FPGA JTAG pins.

In my opinion this is a bug in Vivado’s hardware manager. It could enumerate the list of cables and go through and sequentially initialize the scan chain of each device and identify the devices attached, then disable the JTAG port and move to the next one. However, they appear to have chosen to keep the JTAG port open on all programmers until you select the one you want to use or click on cancel. Unfortunately this behavior is implemented inside of Vivado, and as such, I have no control how it’s implemented. All I can do is report it to the appropriate parties at Xilinx and wait for them to decide whether or not they want to make those chances.

I did find a workaround to allow the HS2 to correctly identify the scan chain in Vivado. Essentially you have to enable the synchronous DPTI port and while keeping it enabled, open Vivado Hardware Manager. Now it should only show the HS2 and it will correctly identify the FPGA because Vivado is no longer controlling the onboard programmer’s JTAG port."

thank you,

Jon
 

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