basic AXI_timer cannot interrupt successfully

[Cynthia]

Hi,

I am using Nexys Video board and fail to trigger interrupt to Microblaze in SDK. So I generate a basic project with only AXI timer, and test with "Peripheral Test" application for xilkernel in SDK, but the test fails as well. 

In Vivado:

1. select the board and create a block design.

2. add microblaze with interrupt controller.  add axi_timer and uartlite.

3. connection as attached figure:

":

4. enable Microblaze exception. generate bitstream.

In SDK:

1. generate bsp for xilkernel, and generate an application of "Peripheral Test" in template, and run. Fail when running "Interrupt Test for axi_timer_0" as shown in figure:

 

In fact, I have tried to interrupt from IP generated by vivado AXI interrupt wrapper, or from customer IP (generated interrupt interface myself), no matter with SENSITIVITY being EDGE_HIGH or LEVEL_HIGH, no matter with concast component or single interrupt, no matter enable exception in bsp or microblaze, neither of them succeed in calling my handler.  

I believe this is not the problem in software (I register handler and enable all interrupts), and even the template application based on basic components still not work. 

Did I miss anything? 

 

Thank you very much!

Cynthia

[artvvb]

@Cynthia

The first thing I see here is the error "Path for project must only have one segment", this means that the directory your project is in is too far away from the root or C: directory for Vivado to handle. You may try moving it and trying again.

Hope this helps,

Arthur

[Cynthia]

@artvvb

Thank you for reply.

This is the error in previous round (because we set run configuration wrong), not this round, I re-test, there is no this error when run.

we also test the same project on Nexys 4 board as well. standalone can past avi_timer test but xilkernel cannot. But standalone cannot trigger the customer IP's interrupt although microblaze exception is enabled in bsp and interrupts are enabled and handler is registered.

Cynthia

 

[AndrewHolzer]

@Cynthia,

I've noticed that you haven't included a MIG in your block design. I suggest that you follow the Getting Started with Microblaze guide for the Nexys Video for help in setting up a base design. I don't have a Nexys Video on hand myself, but I did run through the same process using my Arty. In my first design iteration, I didn't include a MIG and my design failed as yours did. In my next pass through on the design, I dropped in a MIG and regenerated my BSP sources. I ran the test once more and the interrupt test for the timer passed. There will be a pause of a few seconds when testing the axi_timer, so some patience is required.

Let me know if this fixes your issue, and if not I will work with you to find a solution,

AndrewHolzer

[Cynthia]

@AndrewHolzer

Thank you for your help!

We added the MIG and recreated the project following tutorial, the result is wired, it still fails but seems run twice and 2rd time the interrupt test fail as well

 

We doubted maybe because the SDK template simulates interrupt and it's not from the real bus, so axi_timer may not work under xilkernel. So we tried this example using vavido generated IP to interrupt:

https://www.xilinx.com/support/answers/60837.html

However, the interrupt still not caught by Microblaze. 

Looking forward for your help! Thank you so much!

Cynthia

 

 

[AndrewHolzer]

Hi @Cynthia,

I want to thank you for your patience. I've been trying to recreate the results you are seeing but have been unable to do so. Can you send me an image of the block diagram of your design? How are you programming the Nexys Video FPGA? What version of Vivado and Vivado SDK are you using?

One solution that was recommended to me was to go into your project directory and either delete the *.sdk directory or rename it to something else. Once you have done that, go back into Vivado and export design once more and then launch sdk. Go through the process of creating the Peripheral Test application in SDK and launch it. You want to do this because there can be issues when you update the FPGA design in Vivado and then go back to SDK with those revisions. That could be the reason as to why you are seeing this new issue.

Let me know how that goes, and the information I've asked for if this still does not work.

Best of luck,
AndrewHolzer

[Cynthia]

@AndrewHolzer

Thank you so much for you effect on helping me!  I really appreciate it since this problem have bugged me for 2 weeks.

Here are information may help: 

1. board is Digilent Nexys Video, board_files is version A.0, Vivado is version 16.2.  

2. in SDK, I program the FPGA by Xilinx Tools -> Program FPGA

3. I deleted all sdk and re-explore hardware then re-launch SDK, the same result when running Peripheral SelfTest under xilkernel as before.

4. following figure is the block design, you may notice that I add two interrupts into concat (one is from axi_timer(has 2 timers in default), the other is vivado generated IP with interrupt wrapper). Because I try to test interrupts. MIG is included with 200MHz clk. (referred tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze/start   and   https://www.xilinx.com/support/answers/60837.html)

It may be because I connected axi_timer "interrupt" into Microblaze interrupt controller, so the SDK SelfTest run twice (I am testing it). But I do want to catch interrupt from IP through interrupt controller, but never succeed. No matter I enable exceptions of Microblaze in block design or enable exception in bsp (SDK standalone), interrupt from IP would never be caught. That's my main problem.

5. following is the address mapping in above block design:

 

6. followings is C code to enable interrupt in SDK I have tried (commented out code is what I tried as well):

7. I auditing the trace port  of microblaze as well, realizing the interrupt is not caught, so probably the problem is not from interrupt handler (memory problem) but from interrupt controller, or I miss configure something. 

Thank you again for being so patience for helping me. The XPS platform and spartan board I used before did not has such problem, now my project get stuck and I have tested with all tutorials related to IP interrupt but failed (except for Ethernet one). 

 

Cynthia

[AndrewHolzer]

@Cynthia,

Once again I want to thank you for your patience. I want to update here so you aren't left wondering what I've been up to. I have been able to replicate your exact issue where the code executes twice and the interrupt for the timer does not trigger. I've been able to get the peripheral test to succeed on the timer interrupt and exit main, but this was done with a bsp that was made using the standalone OS type. This was done with no changes made to the peripheral test code underneath either the standalone or xilkernal OS type. This leads me to believe that this is an issue with the xilkernal itself.

I haven't quite tracked down the issue yet but I am digging further. I believe I am on the right track here though, and will be reading up on the xilkernal to see if I can find out what the issue is. If the application you have in mind doesn't require the xilkernal OS type, I suggest that you try the standalone OS type and see if that suits your needs. Since you are specifically generating the bsp with the xilkernal type, however, I assume it is necessary in someway.

I'll keep up my work here and update when I've found something. In the meantime take care,
AndrewHolzer

[Cynthia]

@AndrewHolzer

Thank you so much for your help!

May I know if you can succeed in catching interrupt with https://www.xilinx.com/support/answers/60837.html under standalone OS?

I am trying to figure out if the problem is from software lib or Vivado port. Thank you again!

Cynthia

[AndrewHolzer]

@Cynthia,

I've run through the guide that you linked with the standalone OS. I was able to get everything working with the interrupts from the custom IP core being triggered. Some of the code has depricated, like the Xuint32 data types, but if you follow the warnings that SDK gives you you'll figure it out.

You can run the code and see output indicating how many times the interrupt routine has executed. I found that main won't complete execution and never reaches the "Waiting for Interrupts...\n\r" bit. I was able to comment out the xil_printf method in handler() and main was able to complete. Both of these examples demonstrate that the interrupt from the custom IP core is being captured.

Let me know if you have any issues trying this out,
AndrewHolzer

[Cynthia]

@AndrewHolzer

Thank you so much for your help!

We finally find the reason why interrupt not work. When generate Microblaze and interrupt controller together, the "Enable Fast Interrupt Logic" will be clicked. But if generate interrupt controller separately, this box will not be activated. This single is the problem.

After I disable "Enable Fast Interrupt Logic" in interrupt controller, the interrupt can be caught.

Thank you so much again and I can move forward now.

Cynthia

[AndrewHolzer]

@Cynthia,

I am glad to hear that you were able to find what was giving you troubles and want to thank you for posting your solution. Good luck with the rest of your project!

Regards,
AndrewHolzer