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vc26

CMOD A7 35t BRAM Problem

Question

Hi all,

I'm trying to read and write to a BRAM on the CMOD a7 35t (artix 7). However, it always reads back zero. I set it up the same way on the ARTY board and it read back fine. Does anyone know the explanation for this, or have any possible solutions?

Thanks!

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Hi vc26,

You have posted this question in the embedded linux sub-section. Are you using embedded linux(like petalinux) on the Arty and Cmod A7? Could you be more specific on your project. Are you using a soft core processor(microblaze) or HDL(verilog/VHDL). Are you getting any warnings when generating bitstream. If so could you attach a screen shot of the warnings. 

cheers,

Jon

Edited by jpeyron

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Hi Jon,

Oh I apologize for posting in the wrong section. I'm not using embedded linux. 

Should I move the post?

I'm using the microblaze. I've attached the warnings that I'm receiving during generating bitstream. Thanks!

 

Thanks!warnings_bitstream.JPG

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Hi vc26,

Could you attach a zipped folder of your project? Are you trying put the project in flash like your previous posts for the arty?

cheers,

Jon

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Hi Jon,

Eventually, I will put the project in flash, but not at the moment. I can't attach the entire folder because it's too large (32 mb). I've attached a screenshot of the block diagram and a  the code I use to test the bram. Please let me know what other parts you will need. 

Thanks!

block_diagram.JPG

BRAM_app.c

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Hi Jon,

Is the data being written to the BRAM address? I tried to set mem.Membaseaddress to 0xC0000000 (the address of the BRAM), but it didn't work. 

Thanks for all your help!

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Hi Jon, 

I simulated the BRAM by itself and it worked fine. I was wondering if it could be an issue with Vivado and the microblaze interface? Thanks for all your help.

 

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Hi vc26,

I was able to get the provided selftest to work in the below file. I have tried to used your coded process using how the selftest process seems to work. I haven't been able to get that code to be sucessful yet. Hopefully this could be a starting off point. 

cheers,

Jon

Cmod_A7_bram_test.txt

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@jpeyron,

You had to limit the block RAM to 2000?  Is that hexadecimal for 8kB?  Why so little?  I seem to have enough room for 128kB of block RAM memory in one of my own designs with the Artix-7 35T (both on Arty and Basys-3).

Dan

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@D@n

That was the largest i could get to work on the preivous code. It is a left over unused definition currently. I believe that XBram_SelfTest(&mybram,0) uses all of the available bram.

cheers,

Jon

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Hi @vc26,

I have not had time to work further on your SDK coded test of the BRAM. I do know that i was able to run the selftest provided by the SDK(attached above) that tests the BRAM succesfully. Are you not able to run the attached code successfully? 

cheers,

Jon

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Hi @jpeyron,

 

I was able to run the attached code successfully, but have tried using the Xbram library (in addition to just writing to the address) and the functions in there don't work either. I originally thought that I would be able to use the same or similar code for my ARTY and CMOD A7 board because they are both part of the ARTIX 7 group. Thanks for all your help!

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@vc26,

Why would an SRAM (as the CMod A7 has) ever be accessed in the same was as a DDR3 SDRAM (as is on the Arty)?  That doesn't make sense.  They are made of fundamentally different technology, their pin-outs are different, the controllers are fundamentally different ...  SDRAM's are made out of capacitors that lose their charge over time, and hence SDRAM's tend to be able to pack more data per mm^2, but yet they also require more complicated controllers to periodically refresh all of the capacitors.  SRAM's are built out of flip-flops rather than capacitors.  As a result SRAM's take more power, and cannot be packed as tightly, but they don't need refresh cycles.  Hence, SRAM's can often be accessed faster and with simpler controllers

Indeed, I wouldn't put it past you to build your own SRAM controller--were you so interested. 

Were this my own project, I'd look up the part number from the schematic, and Google the data sheet for the SRAM.  I might even look up on OpenCores to see if someone else had built an SRAM controller that looks close enough to what I needed.  (Not sure, I haven't tested it.)

Isn't that what learning Digital logic is all about?  Oh, and ... if the schematic capture approach isn't working for you then ... don't use it.  It's prone to more bugs than anyone wants to admit, and since they are all within someone else (Xilinx's) proprietary code--they are very hard to debug.  Still need a CPU?  MicroBlaze isn't the only FPGA based soft CPU.  Other CPU's include PicoRV, OpenRISC, and even the ZipCPU.  These other CPU's have open source tool chains, and I've been told that Linux runs on OpenRISC as well.

Dan

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@jpeyron,

I used the library xbram_hw.h.

Here are the function definitions.

#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
    XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
#define XBram_ReadReg(BaseAddress, RegOffset) \
    XBram_In32((BaseAddress) + (RegOffset))
 

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@D@n,

I am using the BRAM instantiation for both boards. I didn't know that BRAM was different between the two boards. I'm also pursuing utilizing the cellular ram (SRAM) on the CMOD A7 board as well in place of this. Thanks for your help!

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