Jump to content
  • 0

No Ouput PMOD CLS


jasonbla20

Question

Hello,

I'm using the PMOD CLS, following the instructions found at https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start

My issue is that I cannot get any output on the screen - on power on, I see two vertical lines displayed, so I know it's powered. 

I have the PMOD connected to the JC port in my schematic and physically on the top row of the JC port on the board. I have the CLS configured with JP2 Jumpers MD1 and MD2 are closed, MD0 is open.  JP1 jumper is open, however I've tried it open,closed and across RST. 

I've copied the source files (main.c, pmodCLS.h) to the src folder.  The project builds just fine.

When stepping through the code, I can see it step through the Demorun() function, yet nothing is ever written to the display when I launch on hardware system debugger in SDK.

Can anyone offer any advice?  Have I connected the jumpers properly?  Is there anything else that needs to be configured to run the CLS demo?

I've attached my block design, and the source files of the demo.

Thanks,

Jason

main.c

PmodCLS.h

Block Design.JPG

Link to comment
Share on other sites

3 answers to this question

Recommended Posts

@jasonbla20

The correct jumper setup for the CLS depends on the revision of the Pmod. As described in the reference manual, for a Revision E Pmod CLS, the communication protocol selection jumpers for SPI are still 1,1,0, but this represents disconnected,disconnected,connected.

I have attached photos of a Rev E board in the SPI configuration that I was able to use with the Pmod IPs tutorial, including marking where you can find the revision of your board.

Hope this helps,

Arthur

rev.jpg

jmp[1].jpg

Link to comment
Share on other sites

@artvvb and @jasonbla20,

I was also thinking it may be that the IP core is configured with the new UART pin connection, whereas the PmodCLS follows the old convention. I don't see how the IP core would be pushed to release if that wasn't accounted for and have been working on verifying that the IP core accounts for that discrepancy. If you can verify yourself, then go right ahead. It probably isn't the case, but is something that should be kept in mind when troubleshooting this case.

AndrewHolzer

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...