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ZYBO + PMOD CLS


jasonbla20

Question

Hello, I'm trying to learn how to use the PMOD CLS display on the ZYBO board using Vivado 2016.2. I'm following the tutorial found here:https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start.

I've attached a picture of my block design.  I have three questions:

1. On the PMODCLS_v1_0, what should the frequency of the ext_spi_clk be?

2. Looking though the documentation on the boards PMOD connectors, I see that UART, SPI, and I2C communication happens on the MIO pmod which is the JF pmod.  When choosing which pmod to connect to the CLS in vivado, I only have JA through JE to choose from, so I selected JB.  Is there a problem not having the CLS on the MIO bus?

3.How do I know what physical connections to make between the PMOD and the CLS?  I’ve read the documentation on the CLS pins, and I understand where they should be connected.  My question deals with the PMOD port on the ZYBO – I can’t find any documentation on what the PMOD ports have been mapped to, e.g. SCLK, MOSI, etc.

 

Thanks!

 

 

BlockDesign.PNG

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@jasonbla20

The usual frequency for the ext_spi_clk pin is 50MHz, unless stated otherwise. We're working on making this more obvious in the tutorials. I ran through getting the demo set up, and 50MHz works fine.

As for which Pmod port to use, the CLS pretty much cannot use any ports on the Zybo other that JC and JB, just based on how they physically connect. You could probably use JF with a breadboard, or a Pmod cable, but this will have to use the Zybo's libraries, instead of the one we provide with the IP core, so it may take a few more steps to get working. Short version is that the Zybo hardware Spi is run through different code, and works on different ports, than the FPGA Spi that the IP core sets up. I just used JC with the IP core for my test project.

Lastly, the point of the IP core is that the pinout is abstracted away, if you want to take a look at this, you can right click on the IP core and select Edit in IP packager. The instantiation of the pmod_bridge ip in PmodCLS.v shows how the SPI pins are connected. I've added the relevant lines below. I/O/T are pins for the tristate buffers in the pmod_bridge, so the relevant part of this is the slave select on pin 0 (physical name of 1), MOSI and MISO on pins 1 and 2, and spi clock on pin 3.

(...)
.in0_I(axi_quad_spi_0_SPI_0_SS_I),
.in0_O(axi_quad_spi_0_SPI_0_SS_O),
.in0_T(axi_quad_spi_0_SPI_0_SS_T),
.in1_I(axi_quad_spi_0_SPI_0_IO0_I),
.in1_O(axi_quad_spi_0_SPI_0_IO0_O),
.in1_T(axi_quad_spi_0_SPI_0_IO0_T),
.in2_I(axi_quad_spi_0_SPI_0_IO1_I),
.in2_O(axi_quad_spi_0_SPI_0_IO1_O),
.in2_T(axi_quad_spi_0_SPI_0_IO1_T),
.in3_I(axi_quad_spi_0_SPI_0_SCK_I),
.in3_O(axi_quad_spi_0_SPI_0_SCK_O),
.in3_T(axi_quad_spi_0_SPI_0_SCK_T),
(...)

Hope this helps,

Arthur

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