Jump to content
  • 0

PmodALS


SR93

Question

Hi everyone,

I am trying to follow this example but I have two problems:

- The first one is in Vivado, I am using Vivado 2015.4 and when I add the IP of PmodALS_v1_0 and later I click on Run Connection Automation but the program doesn't connect the pin "ext_spi_clk". What should I do?

- The second one is in SDK, as I indicate, I am following this  example but when I compile the program, I have errors due to SDPI.h. I am trying to download this library but I don't find and I don't know if I am in the right way...

Hope you understand me. Thanks in advance.

SR93!

Link to comment
Share on other sites

4 answers to this question

Recommended Posts

Hello,

I have moved your question to a more appropriate section of the Forum so that other users will be able to find your question more easily.

The main issue you are running into is that the code example you are referencing is not for Vivado; it is for MPIDE, which is a programming environment similar to the Arduino IDE, neither of which will program the FPGA (which FPGA are you working with?).

The code that you will instead need to use is available in the folder you presumably downloaded from our Github to get the PmodALS_v1_0 IP. The particular folder name style you are looking for is explained in step 12 of our Using Pmod IPs Tutorial. It has all of the appropriate library code for the PmodALS to run in the SDK.

As for the ext_spi_clk pin on your block diagram, the Run Connection Automation does not connect that pin (since different Pmods require different clock speeds). I recall the Pmod ALS needing a pretty slow clock speed that Vivado had difficultly generating.

I don't know which FPGA board you have, but you can add an additional output clock to the clocking wizard and configure it to output a 10 MHz clock. It's outside of the the 1 to 4 MHz spec listed in the datasheet for the Pmod ALS, but is within the maximum clock frequency limit (20 MHz) for that same datasheet. You can then connect that 10 MHz clock to the "ext_spi_clk" pin, and from what I've heard from my co-workers, this works for the Pmod ALS. This tutorial is for the Arty (again, I don't know what FPGA you have) but step 3.3 in it's MicroBlaze tutorial shows how you would add an additional clock for the clocking wizard.

Let me know if you have any questions.

Thanks,
JColvin

 

Link to comment
Share on other sites

Thank you for your response @JColvin. I have looked your advice, but I still have problems :( . I am using the Zybo. I followed the tutorial that you recommended me, but it doesn't work. I attached in this post my steps. When I generate my bitstream appear 5 errors. What should I do? 

I am a begginner in this world of Zybo... Thanks in advance for your support.

Best regards.

Captura.JPG

Captura2.JPG

Link to comment
Share on other sites

Hi SR93,

In this case you are using the Zynq processor which is set up a little differently than the microblaze processor. I have attached screen shots that should help with what i am describing below. First add the ZYNQ processor to the empty block design. Next double click into the Zynq IP. In the screen that opens up click into clock configuration and add a second output clock(FCLK_CLK1) and set the clock to 4MHZ.  Run block design without changing any of the settings. Click on the Board tab and right click on in my case (Connector JA). You can choose which pmod port to use. Choose Pmod_out underneath PmodALS_v1_0. next run connection automation. And continue...i.e. validate design, wrapper, generate bitstream, export hardware, launch sdk... Hope this helps!

cheers,

Jon

Zybo_PmodALS_1.jpg

Zybo_PmodALS_2.jpg

Zybo_PmodALS_3.jpg

Zybo_PmodALS_4.jpg

Zybo_PmodALS_5.jpg

zybo_pmodTMP3_6.jpg

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...