CMOD A7 controlled impedance and trace length

[Eliezer]

Hello,

I'm thinking of building a board with CMOD-A7 connected to Gigabit Ethernet PHY chip (like Micrel / Microchip KSZ9031).

as the gigabit signals are using 125Mhz clock and are on both clock edges (250Mhz) I need to keep trace length and 50ohm controlled impedance.

Is there any info about trace length inside the CMOD PCB? pins with 50ohm controlled impedance? (short traces may do the work if I'll place the PHY close to the CMOD)

I'm trying to avoid designing a full FPGA board

[jpeyron]

Hi Eliezer,

 

Our senior layout engineer responded. First and formost a disclaimer: This board was not designed for high speed integration.  Instead it was designed for bread boarding, thus none of the signals out to the connectors are delay matched or impedance controlled. That being said, the impedance on the PIO signals varies between 47.4 and 57.5 ohms.  This depends on which layer it was routed on and if it changes width after it escapes the tiny FPGA package.  Our layout engineer may be able to give you more specifics, if you have certain pins in mind. As for the net lengths, attached is a list of the IO net lengths.  You will need to export a net length file for the FPGA package and add those values in to determine exact delays. I am not sure how you intend to circuit this 1G Ethernet, or how many pins you need, but as you can see from the attached text file the Pmod has the tightest control on length and route. 

 

cheers,

 

Jon

Cmod_A7_netlength.txt

[jpeyron]

Hi Eliezer,

I have reached out to our senior layout engineer about the trace lengths and impedences for the Cmod A7. I will get back to as soon as i get a response.

cheers,

Jon

[Eliezer]

8 hours ago, jpeyron said:

Hi Eliezer,

 

Our senior layout engineer responded. First and formost a disclaimer: This board was not designed for high speed integration.  Instead it was designed for bread boarding, thus none of the signals out to the connectors are delay matched or impedance controlled. That being said, the impedance on the PIO signals varies between 47.4 and 57.5 ohms.  This depends on which layer it was routed on and if it changes width after it escapes the tiny FPGA package.  Our layout engineer may be able to give you more specifics, if you have certain pins in mind. As for the net lengths, attached is a list of the IO net lengths.  You will need to export a net length file for the FPGA package and add those values in to determine exact delays. I am not sure how you intend to circuit this 1G Ethernet, or how many pins you need, but as you can see from the attached text file the Pmod has the tightest control on length and route. 

 

cheers,

 

Jon

Cmod_A7_netlength.txt

Hi,

I'm trying to use an RGMII interface (but I need 2 Phys) so I'll need "only" 2*12 pins for high speed.

Since I can control my own board trace length, and I now have the table above I can put all traces in the right length for delay match.

that said, I still need to find the best pins for my design. I'll need 2 clock input pins with controlled impedance of 50ohm (or close to) and 22 I/O pins with the same controlled impedance. as I believe 47.4ohm controlled impedance is good enough I can only hope to have enough IO's with that controlled impedance.

 

Eliezer

 

[jpeyron]

Hi Eliezer,

Bank 34 should have most of what you need for the 2 clock inputs and i/o pins. Alternatively block 16 has clock inputs as well.

cheer,

jon