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Embedded System Design Flow on Zynq using Vivado for Zybo question


I am not really sure if this is the correct forum or not for this question. I purchased a Zybo board and am trying the Vivado tutorials linked udner the digilent classroom site.



Specifically, I am trying to do the  Embedded System Design Flow on Zynq using Vivado lab2 error using the Zybo board and Vivado 2014.2 webpack. 


When synthesizing the design it says synthesis completed sucessfully but with 16 errors. All of them are a variation of:


  • [Runs 36-287] File does not exist or is not accessible:'c:/Users/David/Desktop/Tutorial_Projects/Xilinx_University_Projects/Embedded_System/lab2/lab2_try1/lab2_try1.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/738df366/hdl/processing_system7_bfm_v2_0_local_params.v'

I looked for the folder and there is no /processing_system7_bfm_v2_0/  folder under xilinx.com in the directory. There is a folder for the processing_system7_v5_4   . I am not sure why the  processing_system7_bfm_v2_0 folder wouldnt have been created.


I would greatly appreciate any guidance or help.




Edited by Josh
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You can post questions like these regarding Zynq in the "FPGA" section of the forum...


Anyways, my bet is that you are running into the frustrating file length problem of Vivado/Windows. Try copying the lab2_try1 folder to a location on your hard drive with fewer characters in the destination. For example, I design all of my 2014.2 vivado projects in C:/sam_work/Vivado_projects/14_2/. This problem stems from the fact that windows cannot handle file destinations that are longer than 256 characters, and Vivado creates a lot of nested folders during synthesis/implementation.

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