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Reading data from MIPI CSI-2 camera sensor


I'm trying to understand how to set up clocks and read data from a MIPI camera sensor.  The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer.  The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets.  In a small MIPI writeup located at http://archive.eetasia.com/www.eetasia.com/ART_8800715969_499489_TA_a466fca2_3.HTM there are 2 statements that are to be taken into consideration when trying to read data:

"The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)"

"The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first."

Using VHDL and Vivado, how do I create logic to successfully read data from this sensor?  I have the following code written (with notes/questions) but I'm pretty sure its wrong.  It was put together based on my limited understanding and reading various other source code that perform similarly:


I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value.  If it is 1, increment the delay value.  This way the delay should always be within +/- 1 of the ideal value.

I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute).  This is probably due to random chance. 

Really need help on this one!

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Looks like you are missing two references: the Xilinx 7-series libraries guide, and the Xilinx 7-series I/O guide.  These'll tell you what you need and how to do what you want.  (You may want the clocking resources guide as well ...)

My best guess is that (assuming the clock is constant), you'll want to use it to drive a PLL, and then an ISERDESE2 to get the data in at DDR rates off of the clock.  You'll then want another (slower) clock that you can read the data back out at about 1/4x the rate or so--something more reasonable than 400MHz.


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