I am working on a unit that has Spartan 6 XC6SLX9 (TGFP144) devices. Each board has 1 Spartan 6 on it and each board is just a copy of the other (briefly, the unit is a 4 channel transmitter and I have each board handling 1 channel - so they are identical copies).
I'm trying to find the best way to program these boards in the field remotely (so I can't rely on removing / attaching cables, pushing buttons etc.)
QUESTION: Can I use the JTAG-SMT2-NC with a full speed USB port (as opposed to a high speed USB port)? The USB hub we use on our motherboard is full speed only. I am not looking for any specific JTAG programming speeds.
Second solution I have is to have an SPI flash for each FPGA and have them all on the same "shared" bus (the SPI flashes would be programmed by my uC on the motherboard). Since the FPGAs take control of the SPI bus on configuration, I'd be "de-coupling" the "shared" bus from the per-board bus with a buffer as shown below:
So when PROGRAM_B is raised to HIGH, the buffer tri-states its outputs (so the shared bus from other FPGAs is no longer in contention).
QUESTION: Thoughts? Does this seem reasonable?
I'm slightly leaning towards the first option - it seems more robust since JTAG was made to do the daisy chaining stuff -- but depends on whether full speed will work.
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Aditya Gaddam
Hi,
I am working on a unit that has Spartan 6 XC6SLX9 (TGFP144) devices. Each board has 1 Spartan 6 on it and each board is just a copy of the other (briefly, the unit is a 4 channel transmitter and I have each board handling 1 channel - so they are identical copies).
I'm trying to find the best way to program these boards in the field remotely (so I can't rely on removing / attaching cables, pushing buttons etc.)
One possible solution is to use this: http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/ on my motherboard and daisy chain JTAG lines as per Xilinx docs.
QUESTION: Can I use the JTAG-SMT2-NC with a full speed USB port (as opposed to a high speed USB port)? The USB hub we use on our motherboard is full speed only. I am not looking for any specific JTAG programming speeds.
Second solution I have is to have an SPI flash for each FPGA and have them all on the same "shared" bus (the SPI flashes would be programmed by my uC on the motherboard). Since the FPGAs take control of the SPI bus on configuration, I'd be "de-coupling" the "shared" bus from the per-board bus with a buffer as shown below:
http://imgur.com/a/jpsjx
So when PROGRAM_B is raised to HIGH, the buffer tri-states its outputs (so the shared bus from other FPGAs is no longer in contention).
QUESTION: Thoughts? Does this seem reasonable?
I'm slightly leaning towards the first option - it seems more robust since JTAG was made to do the daisy chaining stuff -- but depends on whether full speed will work.
Thanks,
Aditya
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