Bandwidth of PMOD ports on Nexys 4 DDR Artix-7

[neil]

Dear All,

I'm completely new to FPGAs but would like to use the PMOD ports on a Nexys 4 DDR Artix-7 FPGA development board to input a high speed digital data stream. I'd like to get to speeds of 100 Mbits per second, or higher if possible. Does anyone know what the bandwidth is for a digital stream on the PMOD ports of this particular FPGA? Or perhaps should I aim to use a different FPGA board?

many thanks, Neil

   

[D@n]

@neil,

PMod's really aren't that high speed of a port.  Using them at high speeds is, I'm sure, not a "supported feature".  However, you might wish to read this discussion on the topic.  While I'm still looking forward to participating in the differential pmod challenge @zygot has offered, I'm still a piece of hardware or two away from actually trying it myself (they're on my next digikey order).  As I remember reading, he was getting roughly 456Mb/s across four differential PMod channels.  I think you will find it a fun challenge to try to get the port up to that speed, or even higher.

Yours,

Dan

[neil]

Dan,

many thanks for your good response and the link, i waited a while in case others responded. But yes i realise Pmod's aren't really designed for this,but there's a possibility it may work, potentially a low cost solution - cost is usually the determining factor in moving forward.

I am interested in the differential single bit transfer, so i'm wondering if the design of the tracks on the Nexys 4 development board for the 8 signal pins from each of the Pmod connectors had had any considerations for minimising the area enclosed (as in a twisted pair), thus minimising electromagnetic pick-up?

What i'm really interested is using the Nexus 4 board to develop a number (up to 16) of differential single bit sampling ADC's (ie the digital output stream from a clocked comparator) each running at up to several hundred Mbits/s. Once digitised there's some novel stuff i can do centred on the physics of coherence, to process the single bits in to something practical.

I may have to back off on the several hundred Mbits/s, but if i can develop the circuit, i can input some known digits into the system and test the speed at which particular error bits are reached.

Do you think i could use the hardware suggested by Zygot to do this multi-channel differential single bit ADC? Or do you think i should be looking at different hardware altogether?

many thanks for your help.

Neil

 

 

[neil]

Dan,

from discussions on this forum so far, probably the Nexys 4 board and the pmod ports are unsuitable for my application. I'm trying to build a 4 receiver channel single bit cross-correlator. That's like an accumulation of XOR operations on all pairs of channels, so for 4 receiver channels, there'll be 6 accumulator registers to store the results. Input data is almost a random digital stream, but you need a correlator to dig signal from the noise. As sensing modality is via correlation, pick up on more than one channel will appear as spurious signal, so i really need differential to minimise the possibility of this. So i'm really looking for an FPGA board with differential input channels/tracks leading to the FPGA, with say a minimum of input 4 channels. (If i can do it with 4 channels, i'd later then like to increase the number of receiver channels) All my data is in single bits, so that makes the mathematics, ie XOR operations simple. However, the data rate is high, hundreds of megabits per second. Could you recommend a suitable FPGA board that i may begin to build this digital correlator around?

many thanks for any help.

Neil

[D@n]

@neil,

Sounds like you want to build a despreader for a wideband spread spectrum signal of some type.  Multiple channels suggests a MIMO implementation, no?  And, like all such, you are going to struggle getting an instant-on synchronizer?  Yeah, you'll want a beefy FPGA for that--even before knowing how difficult your problem is.  Searching over time and frequency is always a challenge.  If knowing an FPGA's clock rate with GPS precision would help, ... I'd be glad to discuss that with you ...

At any rate, the "high speed" ports on the Digilent boards are really the FMC connectors.  Not all of Digilent's boards have them, but the Nexys Video, Genesys, and ZedBoards all have this connector.  The pins on it, at least as far as I understand, are all differential ... so they should be good for some higher speeds.

To get that high speed then down to lower speeds, you'll also want to look into the ISERDESE2 primitive.  (That was my task today ... trying to figure out how to build a 10x deserializer for HDMI ...)

Hope this helps,

Dan

[neil]

Dan,

it's passive (radiometric, thermal or Planck) emission that i'm measuring - so there's no clock on the signal - it's not comms or a mimo radar. In the stage before the FPGA board there will be comparators acting as single bit digitisers, these together with the clock of the FPGA need to be synchronised to a single common low phase noise stable oscillator, so issues are having clock jitter below a few tens of ps, but i gather that's quite possible, if you design it in from the start. 

As i'm really cross-correlating analogue signals by first getting them into the digital format, there is the issue of creating real and imaginary signal components. I can do this either by an analogue down-shift mixer or creating the imaginary from a sampled signal using the Hilbert transform. I've done this successfully in LabVIEW and with commercially built cross-correlators. However, i now want to build the digital sections myself, ie the single bit digitisers and by the FPGA cross-correlator. I'm basically trying to save high development costs by developing this in 'my garage' so to speak.

Putting a heterodyne mixer in front of the whole system enables sensing over the microwave or mm-wave band, and i'm familiar with building such systems.

Colleagues and associates previously used analogue electronic correlators, and these are megasized, as system size (or complexity) scales with the square of the number of receiver channels. The benefit of the FPGA as a digital correlator is that the complexity is all within the FPGA relatively on a microscopic scale, so much more compact and practical. 

Applications i'm looking at are mainly aperture synthesis imaging and some fundamental quantum measurements on microwave or mm-wave photons by using the FPGA to perform signal averaging in a regime where the photon energy (hf) is much less than the background thermal energy (kT).

If i could decide which (beefy) FPGA board to start with i could begin to develop the digital circuity around that, then start programming the FPGA to do the cross-correlation. If i can do this, then i'll be able to build the complete sensor. It's getting the high data rate with minimal cross-talk and pick-up into the FPGA which challenges me. 

Thanks for your advice and i'll take a look at the Nexus Video, Genesys and Zedboards and the ISERDESE2 primitive and see if i can make use of them. Any other advice i'd greatly appreciate, given the above, bigger picture of what i'm doing.

best wishes,

Neil

[D@n]

@neil,

Sounds like what you really want is a proper addition, not an exclusive or, right?  You should be able to do additions at high speed.

Hmm ... other pieces of advice?

1. Be careful how you round and drop bits from fixed point numbers.  If you are not, you'll be adding in a component at DC that wasn't there originally.
2. Getting imaginary signals can be much easier than a full Hilbert transform (which doesn't really exist in practice).  Consider instead using a cordic to bring your real signal down to a complex baseband, and then follow that by lowpass filtering both real and imaginary channels.  The filter design, in my humble opinion, is easier to do, although I think mathematically the two approaches are identical.  (This even applies if your signal is already sampled at it's baseband frequency ...)
3. When you try to do your correlations, you are going to need to start with some limit over what length you wish to correlate over.  This together with the speed of the data you wish to correlate and the number of bits in each sample over will determine the amount of logic you need.  If you are correlating over a long enough interval, FFT's start to become the optimal method.
4. To get a logic estimate, try building and simulating your design first.  When it passes whatever simulator you have, then apply the result to Vivado to see how many of each of the various components you need.  Multiply the result by two, and then look for what FPGA meets your requirements.
5. I'd offer some advice regarding the ISERDESE2 but ... I'm just building with my first one today.  Ask me in a month or two and I should be able to give you some thoughts.

Dan

[neil]

Dan,

i see your point about the logic gate. It's called cross-correlation, but there's no delay, so from the mathematical definition of correlation, its referred to as a zero lag correlator, which is just a straight forward multiplication of the sampled electric fields. As it's single bit digitisation, the signal is either +ve or -ve. So for +ve X +ve = +ve; -ve X -ve = +ve, +ve X -ve = -ve; -ve X +ve = -ve. If 0 represents -ve and 1 represents +ve, then the truth table would be a 'not exclusive or', NXOR. 

In the single bit digitisation using the comparator, a trick to avoid the build up of DC is to employ a feedback loop to the bias on the comparator. As what you're measuring is AC, the long term average of the single bit digitisation should be 0.5, ie 50% 1's and 50% 0's. So adjust the bias to ensure this is the case.

When you say cordic - i guess you mean using a matched mixer pair to down-shift (LO of one having pi/2 phase shift) so you create sin and cosine channels, then do single bit digitisation in each of these channels. The digital solution would be something like fs/4 digitisation followed by alternate bit reversal to create the imaginary component (a standard digital trick to implement a good approximation to the Hilbert transform). Manufacturers to date have preferred the former, as they viewed as less risky. To do the latter might require still faster single bit digitisation.  

Dont quite follow the FFT you refer to - the cross-correlations would be accumulated for tens of milliseconds, so for ns sample times, there are accumulations of tens of millions of these fast multiplies. As the cross-mulitply is complex there are 4 components, and for n receiver channels there are n(n-1)/2 cross correlations, so the number of accumulators is just the product of these, ie 2n(n-1). There is no frequency encoding of data and from one sample to the next there is no phase coherence - it's passive radiometric emission - it would be different for radar, but this isnt radar, so i'm not sure if an FFT would be useful. Have i missed a trick here by using an FFT in some way?

Quite - i'd like to begin to model this in something like VHDL - does this need to be FPGA board specific, i've never programmed this before, what software should i use for this?

many thanks for your good points and advice.

best wishes,

Neil

[D@n]

@neil,

Sounds like you know your application better than I do. 

So, basically, inside the FPGA you would need to first build an ISERDESE2 to take the initial data rate down to something you can handle.  So, instead of dealing with single data bits at Gbps speeds, you'd then be dealing with 2-14 data bits (your choice, but I think the hardware maxes out at 14) at speeds 2x to 14x slower than your incoming rate.  This can be a hassle, 'cause you then need to figure out how to think about your single samples in a stream processing engine where you process them all at once, still ... it's quite doable.  (If you haven't purchased hardware yet, then I might suggest you plan on using the ISERDESE2 at a 14x rate ... that will then help you focus your design methodologies on 14-bit words, while keeping your options open for later higher speed ops.)

If you are doing a zero lag correlator, then my comments about needing massive computer power may not be appropriate.  I'm used to needing to search for the correct lag (and frequency offset), and building the ambiguity function can be quite painful.

Still, I think you misunderstood my comment about the CORDIC.  So ... let's back up.  If you have only single bit data, a CORDIC wouldn't be needed.  Simpler bit ops would be sufficient.  Still, my thought was you would take your already digitized input bits and multiply them by a complex exponential at -pi/2 frequency.  This would move your sampled real signal to DC with a complex baseband, from whence you could apply (still digital) filters to remove the (now highpass) information that would've been taken care of by your Hilbert transform.  I suppose you could alternative shift the lowpass filters up in frequency and skip the downconversion but ... I doubt it really matters which choice you make there.

Likewise, my comments about a DC bias in your results were not based upon the idea of a DC bias in your sampling hardware, but rather a DC bias in how you build your correlator digital software.  Specifically, look at how you handle truncation.  Consider what you do if you have a 16'bit accumulator value and you need to drop it down to 8-bits.  If you always round up whenever your exactly half way between sample points, then you'll get a DC bias in your results.

Finally, regarding simulating things before settling on a board.  I'd highly recommend it.  With just about all of my designs, I can simulate the entire (non-Xilinx specific portion) of the design using Verilator.  This allows me to simulate all the hardware my design interacts with (I'll be building a video output soon, but I also have cycle accurate simulations for flash memory, FFT's, a ZipCPU, an SD card, a serial port to interact with the design, and more.)  Further, I interact with my designs over TCP/IP, whether with an actual design or a simulated design, so ... my host interaction software can't tell if it's talking to a board itself, or just the simulation.  (I challenge you to find a MicroBlaze implementation that allows open source simulation ...)  Sorry, it doesn't work for VHDL.  I'm told there are other solutions that do work for VHDL, but when I've looked into them they've never been as rich.  At least ... this is where I would start.

Hope that helps,

Dan

[neil]

Dan,

thank you for those suggestions, these boards, the FMC connector and the ISERDESE2 gives me something to think about.

But just looking back at the PMOD ports on the Nexys 4 DDR Artix-7 board, then one of the 5 PMOD ports on this board is what they refer to as the JXADC PMOD port, which according to Digilent literature, "can be configured either as analog input or digital input-output." You can see the differential signal tracks on the board leading from the PMOD connector. Do you think then i could use the 8 inputs on this particular port to act as 4 high-speed digital differential inputs? If that is the case then as least i could start to build a cross-correlator for 4 receiver channels.

many thanks,

Neil

[D@n]

@neil,

@zygot had made a comment some time ago that the XADC pins really worn' good enough for high speed I/O.  I haven't dug into what he was referencing.  I will note that the circuitry on the XADC pins is different from that of of a normal PMod, so ... they wouldn't be my first choice if I had a choice.  Further, I think the XADC0 pin on the Nexys-DDR has a low-pass filter on it--not at all what you'd want to use for high speed.  You might be stuck with needing different hardware if you really want the high speed ports.

Dan

P.S. Don't tell @zygot (yet) ... but I think I can make an interface that'll get nearly 150MB/s (that's mega-Bytes per second) using a differential PMod port.  I wouldn't want you to tell him yet, 'cause it's a work in progress, but I do intend to smash his record in due time ...  

[neil]

Dan,

many thanks for recommendations, in summary for a cross-correlator:

 NexysVideo: This board has two Pmod ports (JB & JC) with differential routing to the Artix-7 FPGA, but according to the board schematic no anti-aliasing RC filter, but 100 Ohm characteristic impedance across the differential pair, so would provide 8 differential pair inputs. This means you'll have to do you're own Nyquist filtering - no real problem there, if you build into analogue front-end. Hopefully multi 100's MHz of bandwidth could be achieved.

The FMC connector indicates 34 differential channels - so this would enable a cross-correlator four times as many inputs. However the question is whether the Artix-7 FPGA could keep up with the high rate of xor operations (done say by a look up table) for the cross-correlator, as the complexity of the correlator goes as the square of the number of input channels.

ZedBoard: Has two Pmod ports (JC1 & JD1) I/O differentially routed to the Zynq FPGA to support LVDS to 525 Mbps (board schematic indicating no anti-aliasing filtering), so that's a total of 8 differential pairs.  Do you think the data rate 525 Mbps is the total data rate for each Pmod port, or for each differential channel pair?

The FMC connector indicates 34 differential channels - so this would enable a cross-correlator four times as many inputs, however could the Zynq FPGA device could keep up with the high rate of xor operations?

Genesys2:  Has two Pmod port (JA & JB) differentially routed to the Kintex-7 FPGA for >10 MHz LVDS_25 inputs, so that's a total of 8 differential pairs. From the board schematic there's no series resistance and shunt capacitance, presumably to get large bandwidth. 

The FMC connector has 400 pins which includes 80 differential signaling pairs so that could be the basis for quite a powerful multi-channel cross-correlator. The question is what kind of parallel data rate through the systems could be had if there were 80 receiver channels fed the 80 differential signal pair? Presumably the Kintex-7 would have significantly more power than the Zynq and Artix-7?

Could you say anything about the relative suitabilities of the Virtex-7, Zynq and the Genesys2 for doing large numbers of simple xor operations? I'm only really interested the FPGA realestate performing these operations, and not really much else, save perhaps extracting from the internal 450 MHz clock and external clock to clock front end comparators and analogue heterodyne receiver local oscillators.

best wishes,

Neil

 

 

 

[neil]

If the FMC connector were used to input the data (as could be trialed on a Nexys Video board) and it were successful, this might lead the way to developing cross-correlators having hundreds of channels by using the FMC connectors to input data to some of the more powerful FPGA development boards, say using the Virtex-7 FPGA.

The obvious question there is, when the FMC connector to an FPGA development board is quoted as having 34 or 80 differential inputs, what is the bandwidth of say a single differential pair from the connector to the FPGA? (i need bandwidths of hundreds of MHz for the cross-correlator) I take it there are no shunt capacitors or series resistances to bandwidth limit the input,except some stray capacitance of the track. Could anyone suggest what the bandwidth might be?

thank you,

Neil

 

 

this then could be extended to some of the more powerful FPGA development boards to do , this may