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Hendrik

Basys3 blinking led

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I tried to do a the blinking LED(at 1 Hz) using VHDL on Vivado 2016.4 with no luck.How should I setup the xdc constraint file to accomplish this,specifically the clock?

Thanks,

H

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@Hendrik,

Start with the XDC file from the Basys resource page, and uncomment every line that references the clock or the LED(s) by removing the "#" from the beginning of the line.  Your next step will involve changing the names "clk" and "led[0]" to ... whatever names you gave them in your top level design.

Vivado will complain if you have pins defined in your XDC file (uncommented) that are not used in your design.

Dan

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Hi Dan,

I miss something.I did uncomment the clock and LED lines in the XDC file.Where do I specify the clock freq?  ...When I run the simulation I see no clock pulse on the simulation.

I replaced the "clk" with "clk_1" and the "led[0]"with "blinker_0"

 

SEE TOP LEVEL BELOW...I did not include the architecture part of the design by the way there is no error in that part of the code I get green light.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

 

entity blinker_led2 is
    Port ( clk_1 : in STD_LOGIC;
           blinker_o : out STD_LOGIC);
end blinker_led2;

 

 

 

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Dan,

Yes I did, sorry that was a typo it is "blinker_o"..

Still get the same results.Any other ideas??Again the top level program seem to be good I get no errors.(green status).

1.In Vivado(2016.4) where do I see the clk freq assigned for the project?(will it always be 450 MHz)with an oss(100MHz) connected to pin W5 from what I can see on the schematic.

2.Can I send you the XDC and top level design maybe you can run/check it out on your end?

Thanks,

H

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@Hendrik,

Yeah, let's do this: Go ahead and attach your XDC and your Verilog file to your reply post, and I'll look to see if/what you might be missing.

As for the speed of the clock, it should be defined in the XDC file.  In mine, I have a line that looks like

create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk_100mhz]

and defines my clock speed as 10ns with a 50% duty cycle (100MHz)--but then again, I'm naming my clock pin i_clk_100mhz.  Your name might be different.

Dan

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